git: b57a571a0019 - main - arm64: Split out accessing special registers

The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=b57a571a001958febec042e15c571c5074ce44ce

commit b57a571a001958febec042e15c571c5074ce44ce
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2025-10-27 10:56:17 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2025-10-27 11:36:17 +0000

    arm64: Split out accessing special registers
    
    We shouldn't need to include armreg.h just to access special registers
    that are not defined in this file. Split out the parts that should be
    common with arm64.h and hypervisor.h.
    
    Reviewed by:    emaste
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D53324
---
 sys/arm64/include/_armreg.h    | 56 ++++++++++++++++++++++++++++++++++++++++++
 sys/arm64/include/armreg.h     | 20 ++-------------
 sys/arm64/include/hypervisor.h |  2 ++
 3 files changed, 60 insertions(+), 18 deletions(-)

diff --git a/sys/arm64/include/_armreg.h b/sys/arm64/include/_armreg.h
new file mode 100644
index 000000000000..7aa3c358b327
--- /dev/null
+++ b/sys/arm64/include/_armreg.h
@@ -0,0 +1,56 @@
+/*-
+ * Copyright (c) 2013, 2014 Andrew Turner
+ * Copyright (c) 2015,2021 The FreeBSD Foundation
+ *
+ * Portions of this software were developed by Andrew Turner
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#if !defined(_MACHINE_ARMREG_H_) && \
+    !defined(_MACHINE_HYPERVISOR_H_)
+#error Do not include this file directly
+#endif
+
+#ifndef _MACHINE__ARMREG_H_
+#define	_MACHINE__ARMREG_H_
+
+#define	__MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)			\
+    S##op0##_##op1##_C##crn##_C##crm##_##op2
+#define	_MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)			\
+    __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)
+#define	MRS_REG_ALT_NAME(reg)						\
+    _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)
+
+
+#define	READ_SPECIALREG(reg)						\
+({	uint64_t _val;							\
+	__asm __volatile("mrs	%0, " __STRING(reg) : "=&r" (_val));	\
+	_val;								\
+})
+#define	WRITE_SPECIALREG(reg, _val)					\
+	__asm __volatile("msr	" __STRING(reg) ", %0" : : "r"((uint64_t)_val))
+
+#define	UL(x)	UINT64_C(x)
+
+#endif /* !_MACHINE__ARMREG_H_ */
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index aca3d4c07450..aa9b672ad85a 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -34,25 +34,9 @@
 #ifndef _MACHINE_ARMREG_H_
 #define	_MACHINE_ARMREG_H_
 
-#define	INSN_SIZE		4
-
-#define	__MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)			\
-    S##op0##_##op1##_C##crn##_C##crm##_##op2
-#define	_MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)			\
-    __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)
-#define	MRS_REG_ALT_NAME(reg)						\
-    _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)
-
+#include <machine/_armreg.h>
 
-#define	READ_SPECIALREG(reg)						\
-({	uint64_t _val;							\
-	__asm __volatile("mrs	%0, " __STRING(reg) : "=&r" (_val));	\
-	_val;								\
-})
-#define	WRITE_SPECIALREG(reg, _val)					\
-	__asm __volatile("msr	" __STRING(reg) ", %0" : : "r"((uint64_t)_val))
-
-#define	UL(x)	UINT64_C(x)
+#define	INSN_SIZE		4
 
 /* AFSR0_EL1 - Auxiliary Fault Status Register 0 */
 #define	AFSR0_EL1_REG			MRS_REG_ALT_NAME(AFSR0_EL1)
diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index 8feabd2b981b..7d405e63cd8d 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -30,6 +30,8 @@
 #ifndef _MACHINE_HYPERVISOR_H_
 #define	_MACHINE_HYPERVISOR_H_
 
+#include <machine/_armreg.h>
+
 /*
  * These registers are only useful when in hypervisor context,
  * e.g. specific to EL2, or controlling the hypervisor.