From nobody Sun Mar 16 02:35:18 2025 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4ZFhzB6ZPmz5qbXL; Sun, 16 Mar 2025 02:35:18 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4ZFhzB5WRVz46Bq; Sun, 16 Mar 2025 02:35:18 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1742092518; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=QaPSPxRRifNtc+OAijcIb4KXrQXLN5P4CCmejDosU78=; b=gK/o7GXd1zfLr2WBO3e7Nm1714cxSZlD38G6u07RvJQ56ib8PYLHjKeeOihrOqMcWYkBGD 7A/nHQI9nWJt4uHW+gzC5EGQlP+AeNI5lduWDxFnSj/wUdJUz915FOBJ4n6UYZqoM09ggP PGO9oY4T/dogpFM2CwmE5kCp3mmG5ZKz//o99ir7XhKzjkF8oKq9zYaiYaLoTH/Lhk+ZpJ r9c82SjjSSrUrbvrJO1L5e2Mkqze+1LBOIhjm8sVQGCOGfq1JLqk5I3cy9sQ3Y+6fy7mwA 5nmG8Lnaw2AFwq2bnWa0B4PupjN1b3LriVK0jzyT/s0gKpgqt65/I4v18pvwLg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1742092518; a=rsa-sha256; cv=none; b=o3/w0r+TEkl+3uOlxvRMXiEDCgaZKfqgfmp9EnWeFnnKVnI9NPKUtY8QNMZnICIUclZYqa a/rV79r0aD3SmmIK9JrrM8AH+NABfyn1NyH0RHs+PfyCM61x0TK60YrHerCZLs39GYt4X+ 3ZN8u3ClDCZYkmHdnowyBik0YcvF/pNe5lqUVpqPq/C7VMO8yA8hbWzUg3dDHC0ZT1A/5k moq4bMKnBNL6qkLOQMzt99uA+x/Lj2Ul+usv7cWEp+JLc8ZrwP3698G9gb0YoKb4QH6blo qyYw5YwZYOEOSs1KHll8UwAk+j7cJjuMBkAizp/8iB+ko+QJqi5iMKqRnmas5w== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1742092518; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=QaPSPxRRifNtc+OAijcIb4KXrQXLN5P4CCmejDosU78=; b=UjGYlaGj6XODMR8GSjRIVZgn6/BhJoSWiydc0S9oCLMiNvCAvTgMan1BytpEpWJiVasxjJ uEUQvlFCp+LR4n2NTX9zmtGT+LkHrO7idhPvtmMIkGbzeh9+c+Cg/jsn/AuDXNiLpI9qpK ahIAyWkCS5F8wMcqEAQ9wlDckuKzLucPvNfrXw8PQSnYlW1MvDWbJqxZlOK8FIrQSL3vBW ICR76CLKFnbWL0EBnZTickDeQYvc1KE3m1OzewhIJ1pvFkiA3jADtZDdUE4cr19LOc9cK5 GAa0g3iz44hxL8xe+mkyXnJMDKkXfhTKQWBctZ05Jg76pzwWJMeve46vXNIfwQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4ZFhzB55SkzhPB; Sun, 16 Mar 2025 02:35:18 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 52G2ZII2026411; Sun, 16 Mar 2025 02:35:18 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 52G2ZIgC026408; Sun, 16 Mar 2025 02:35:18 GMT (envelope-from git) Date: Sun, 16 Mar 2025 02:35:18 GMT Message-Id: <202503160235.52G2ZIgC026408@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Navdeep Parhar Subject: git: 011e3d0b8b90 - main - cxgbe(4): Perform Conventional Reset instead of FLR on the device. List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: np X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 011e3d0b8b90a4330f14b2cb7da45ed7b805ed10 Auto-Submitted: auto-generated The branch main has been updated by np: URL: https://cgit.FreeBSD.org/src/commit/?id=011e3d0b8b90a4330f14b2cb7da45ed7b805ed10 commit 011e3d0b8b90a4330f14b2cb7da45ed7b805ed10 Author: Navdeep Parhar AuthorDate: 2024-12-07 08:00:49 +0000 Commit: Navdeep Parhar CommitDate: 2025-03-16 01:16:42 +0000 cxgbe(4): Perform Conventional Reset instead of FLR on the device. The driver uses bus_reset_child on its parent to reset itself but that performs an FLR whereas the hardware needs a Conventional Reset[1] for full re-initialization. Add routines that perform conventional hot reset and use them instead. The available reset mechanisms are: * PCIe secondary bus reset (default) * PCIe link bounce hw.cxgbe.reset_method can be used to override the default. The internal PL_RST is also available but is for testing only. [1] 6.6.1 in PCI Express® Base Specification 5.0 version 1.0 MFC after: 1 month Sponsored by: Chelsio Communications --- sys/dev/cxgbe/t4_main.c | 137 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 118 insertions(+), 19 deletions(-) diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c index 6ee839151db0..20df6a97aa87 100644 --- a/sys/dev/cxgbe/t4_main.c +++ b/sys/dev/cxgbe/t4_main.c @@ -633,6 +633,10 @@ static int t4_reset_on_fatal_err = 0; SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN, &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors"); +static int t4_reset_method = 1; +SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_method, CTLFLAG_RWTUN, &t4_reset_method, + 0, "reset method: 0 = PL_RST, 1 = PCIe secondary bus reset, 2 = PCIe link bounce"); + static int t4_clock_gate_on_suspend = 0; SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN, &t4_clock_gate_on_suspend, 0, "gate the clock on suspend"); @@ -2535,40 +2539,135 @@ t4_reset_post(device_t dev, device_t child) return (0); } -static int -reset_adapter_with_pci_bus_reset(struct adapter *sc) -{ - int rc; - - mtx_lock(&Giant); - rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0); - mtx_unlock(&Giant); - return (rc); -} - static int reset_adapter_with_pl_rst(struct adapter *sc) { - suspend_adapter(sc); - /* This is a t4_write_reg without the hw_off_limits check. */ MPASS(sc->error_flags & HW_OFF_LIMITS); bus_space_write_4(sc->bt, sc->bh, A_PL_RST, F_PIORSTMODE | F_PIORST | F_AUTOPCIEPAUSE); pause("pl_rst", 1 * hz); /* Wait 1s for reset */ + return (0); +} - resume_adapter(sc); +static int +reset_adapter_with_pcie_sbr(struct adapter *sc) +{ + device_t pdev = device_get_parent(sc->dev); + device_t gpdev = device_get_parent(pdev); + device_t *children; + int rc, i, lcap, lsta, nchildren; + uint32_t v; - return (0); + rc = pci_find_cap(gpdev, PCIY_EXPRESS, &v); + if (rc != 0) { + CH_ERR(sc, "%s: pci_find_cap(%s, pcie) failed: %d\n", __func__, + device_get_nameunit(gpdev), rc); + return (ENOTSUP); + } + lcap = v + PCIER_LINK_CAP; + lsta = v + PCIER_LINK_STA; + + nchildren = 0; + device_get_children(pdev, &children, &nchildren); + for (i = 0; i < nchildren; i++) + pci_save_state(children[i]); + v = pci_read_config(gpdev, PCIR_BRIDGECTL_1, 2); + pci_write_config(gpdev, PCIR_BRIDGECTL_1, v | PCIB_BCR_SECBUS_RESET, 2); + pause("pcie_sbr1", hz / 10); /* 100ms */ + pci_write_config(gpdev, PCIR_BRIDGECTL_1, v, 2); + pause("pcie_sbr2", hz); /* Wait 1s before restore_state. */ + v = pci_read_config(gpdev, lsta, 2); + if (pci_read_config(gpdev, lcap, 2) & PCIEM_LINK_CAP_DL_ACTIVE) + rc = v & PCIEM_LINK_STA_DL_ACTIVE ? 0 : ETIMEDOUT; + else if (v & (PCIEM_LINK_STA_TRAINING_ERROR | PCIEM_LINK_STA_TRAINING)) + rc = ETIMEDOUT; + else + rc = 0; + if (rc != 0) + CH_ERR(sc, "%s: PCIe link is down after reset, LINK_STA 0x%x\n", + __func__, v); + else { + for (i = 0; i < nchildren; i++) + pci_restore_state(children[i]); + } + free(children, M_TEMP); + + return (rc); +} + +static int +reset_adapter_with_pcie_link_bounce(struct adapter *sc) +{ + device_t pdev = device_get_parent(sc->dev); + device_t gpdev = device_get_parent(pdev); + device_t *children; + int rc, i, lcap, lctl, lsta, nchildren; + uint32_t v; + + rc = pci_find_cap(gpdev, PCIY_EXPRESS, &v); + if (rc != 0) { + CH_ERR(sc, "%s: pci_find_cap(%s, pcie) failed: %d\n", __func__, + device_get_nameunit(gpdev), rc); + return (ENOTSUP); + } + lcap = v + PCIER_LINK_CAP; + lctl = v + PCIER_LINK_CTL; + lsta = v + PCIER_LINK_STA; + + nchildren = 0; + device_get_children(pdev, &children, &nchildren); + for (i = 0; i < nchildren; i++) + pci_save_state(children[i]); + v = pci_read_config(gpdev, lctl, 2); + pci_write_config(gpdev, lctl, v | PCIEM_LINK_CTL_LINK_DIS, 2); + pause("pcie_lnk1", 100 * hz / 1000); /* 100ms */ + pci_write_config(gpdev, lctl, v | PCIEM_LINK_CTL_RETRAIN_LINK, 2); + pause("pcie_lnk2", hz); /* Wait 1s before restore_state. */ + v = pci_read_config(gpdev, lsta, 2); + if (pci_read_config(gpdev, lcap, 2) & PCIEM_LINK_CAP_DL_ACTIVE) + rc = v & PCIEM_LINK_STA_DL_ACTIVE ? 0 : ETIMEDOUT; + else if (v & (PCIEM_LINK_STA_TRAINING_ERROR | PCIEM_LINK_STA_TRAINING)) + rc = ETIMEDOUT; + else + rc = 0; + if (rc != 0) + CH_ERR(sc, "%s: PCIe link is down after reset, LINK_STA 0x%x\n", + __func__, v); + else { + for (i = 0; i < nchildren; i++) + pci_restore_state(children[i]); + } + free(children, M_TEMP); + + return (rc); } static inline int reset_adapter(struct adapter *sc) { - if (vm_guest == 0) - return (reset_adapter_with_pci_bus_reset(sc)); - else - return (reset_adapter_with_pl_rst(sc)); + int rc; + const int reset_method = vm_guest == VM_GUEST_NO ? t4_reset_method : 0; + + rc = suspend_adapter(sc); + if (rc != 0) + return (rc); + + switch (reset_method) { + case 1: + rc = reset_adapter_with_pcie_sbr(sc); + break; + case 2: + rc = reset_adapter_with_pcie_link_bounce(sc); + break; + case 0: + default: + rc = reset_adapter_with_pl_rst(sc); + break; + } + if (rc == 0) + rc = resume_adapter(sc); + return (rc); } static void