git: 43fa7b907e9c - main - amdiommu: add register definitions from IOMMU spec 48882 rev. 3.10

The branch main has been updated by kib:

URL: https://cgit.FreeBSD.org/src/commit/?id=43fa7b907e9cc5ce365afd05775349d199fc2eb4

commit 43fa7b907e9cc5ce365afd05775349d199fc2eb4
Author:     Konstantin Belousov <kib@FreeBSD.org>
AuthorDate: 2025-03-02 01:23:41 +0000
Commit:     Konstantin Belousov <kib@FreeBSD.org>
CommitDate: 2025-03-02 01:23:41 +0000

    amdiommu: add register definitions from IOMMU spec 48882 rev. 3.10
    
    Most important for us is the max interrupt remapping count report in the
    EFR2 register.
    
    Sponsored by:   Advanced Micro Devices (AMD)
    Sponsored by:   The FreeBSD Foundation
    MFC after:      1 week
---
 sys/x86/iommu/amd_reg.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/sys/x86/iommu/amd_reg.h b/sys/x86/iommu/amd_reg.h
index 37375b3fa7b5..53b8b0cb42fc 100644
--- a/sys/x86/iommu/amd_reg.h
+++ b/sys/x86/iommu/amd_reg.h
@@ -186,6 +186,9 @@
 #define	AMDIOMMU_CTRL_MARC_EN		0x0000010000000000ull	/* Memory Addr Routing En */
 #define	AMDIOMMU_CTRL_BLKSTOPMRK_EN	0x0000020000000000ull	/* Block StopMark En */
 #define	AMDIOMMU_CTRL_PPRAUTORESPA_EN	0x0000040000000000ull	/* PPR Auto Resp Always En */
+#define	AMDIOMMU_CTRL_NUMINTRREMAP_MASK	0x0000180000000000ull	/* Remapping MSI mode */
+#define	AMDIOMMU_CTRL_NUMINTRREMAP_512	0x0000000000000000ull	/* 512 max */
+#define	AMDIOMMU_CTRL_NUMINTRREMAP_2048	0x0000080000000000ull	/* 2048 max */
 #define	AMDIOMMU_CTRL_EPH_EN		0x0000200000000000ull	/* Enh PPR Handling En */
 #define	AMDIOMMU_CTRL_HADUP_MASK	0x0000c00000000000ull	/* Access and Dirty in host PT */
 #define	AMDIOMMU_CTRL_GDUP_DIS		0x0001000000000000ull	/* Dis Dirty in guest PT */
@@ -256,6 +259,21 @@
 #define	AMDIOMMU_CMDEVS_PPROVRFLWEB	0x00020000
 #define	AMDIOMMU_CMDEVS_PPROVRFLWE	0x00040000
 
+/*
+ * IOMMU Extended Feature2 register fields.
+ * All currently defined bits are RO.
+ */
+#define	AMDIOMMU_EFR2_TMPMSUP		0x0000000000000004ull	/* Tired Mem Migration */
+#define	AMDIOMMU_EFR2_GCR3TRPM		0x0000000000000008ull	/* GPA based GCR3 pointer in DTE */
+#define	AMDIOMMU_EFR2_GAPPID		0x0000000000000010ull	/* masking of GAPIC PPI */
+#define	AMDIOMMU_EFR2_SNPAVIC_MASK	0x00000000000000e0ull	/* SNP-enabled Adv intr features */
+#define	AMDIOMMU_EFR2_SNPAVIC_NO	0x0000000000000000ull	/* No features supported */
+#define	AMDIOMMU_EFR2_SNPAVIC_REMAPV	0x0000000000000020ull	/* Intr remapping with GVAPIC */
+#define	AMDIOMMU_EFR2_NUMINTRREMAP_MASK	0x0000000000000300ull	/* Number of remapped intr per dev */
+#define	AMDIOMMU_EFR2_NUMINTRREMAP_512	0x0000000000000000ull	/* 512 */
+#define	AMDIOMMU_EFR2_NUMINTRREMAP_2048	0x0000000000000100ull	/* 2048 */
+#define	AMDIOMMU_EFR2_HTRANGEIGN	0x0000000000000800ull	/* HT range is regular GPA */
+
 /*
  * Device Table Entry (DTE)
  */