git: 9eddbaa5bba2 - main - bhyve: add GVT-d support for graphics gen 11 and newer

The branch main has been updated by corvink:

URL: https://cgit.FreeBSD.org/src/commit/?id=9eddbaa5bba20c1a276d4711a4e9271e5f200ee1

commit 9eddbaa5bba20c1a276d4711a4e9271e5f200ee1
Author:     Corvin Köhne <corvink@FreeBSD.org>
AuthorDate: 2023-12-15 11:29:19 +0000
Commit:     Corvin Köhne <corvink@FreeBSD.org>
CommitDate: 2025-08-05 14:02:08 +0000

    bhyve: add GVT-d support for graphics gen 11 and newer
    
    The BDSM (Base Data Stolen Memory) register changed. Older generations are
    using a 32 bit register. On newer generations a different register address is
    used and the size was changed to 64 bit to permit allocating graphics stolen
    memory above 4 GB. Bhyve has to detect that and properly emulate the correct
    register.
    
    Reviewed by:            jhb, markj
    MFC after:              1 week
    Sponsored by:           Beckhoff Automation GmbH & Co. KG
    Differential Revision:  https://reviews.freebsd.org/D45338
---
 usr.sbin/bhyve/amd64/pci_gvt-d.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/usr.sbin/bhyve/amd64/pci_gvt-d.c b/usr.sbin/bhyve/amd64/pci_gvt-d.c
index e506b75e77fe..630c5caf4b7b 100644
--- a/usr.sbin/bhyve/amd64/pci_gvt-d.c
+++ b/usr.sbin/bhyve/amd64/pci_gvt-d.c
@@ -33,6 +33,7 @@
 #define PCI_VENDOR_INTEL 0x8086
 
 #define PCIR_BDSM 0x5C	   /* Base of Data Stolen Memory register */
+#define PCIR_BDSM_GEN11 0xC0
 #define PCIR_ASLS_CTL 0xFC /* Opregion start address register */
 
 #define PCIM_BDSM_GSM_ALIGNMENT \
@@ -64,12 +65,37 @@ set_bdsm_gen3(struct pci_devinst *const pi, vm_paddr_t bdsm_gpa)
 	return (0);
 }
 
+static int
+set_bdsm_gen11(struct pci_devinst *const pi, vm_paddr_t bdsm_gpa)
+{
+	struct passthru_softc *sc = pi->pi_arg;
+	uint64_t bdsm;
+	int error;
+
+	bdsm = pci_host_read_config(passthru_get_sel(sc), PCIR_BDSM_GEN11, 8);
+
+	/* Protect the BDSM register in PCI space. */
+	pci_set_cfgdata32(pi, PCIR_BDSM_GEN11,
+	    bdsm_gpa | (bdsm & (PCIM_BDSM_GSM_ALIGNMENT - 1)));
+	pci_set_cfgdata32(pi, PCIR_BDSM_GEN11 + 4, bdsm_gpa >> 32);
+	error = set_pcir_handler(sc, PCIR_BDSM_GEN11, 8, passthru_cfgread_emulate,
+	    passthru_cfgwrite_emulate);
+	if (error) {
+		warnx("%s: Failed to setup handler for BDSM register!\n", __func__);
+		return (error);
+	}
+
+	return (0);
+}
+
 struct igd_ops {
 	int (*set_bdsm)(struct pci_devinst *const pi, vm_paddr_t bdsm_gpa);
 };
 
 static const struct igd_ops igd_ops_gen3 = { .set_bdsm = set_bdsm_gen3 };
 
+static const struct igd_ops igd_ops_gen11 = { .set_bdsm = set_bdsm_gen11 };
+
 struct igd_device {
 	uint32_t device_id;
 	const struct igd_ops *ops;
@@ -105,6 +131,17 @@ static const struct igd_device igd_devices[] = {
 	INTEL_CML_IDS(IGD_DEVICE, &igd_ops_gen3),
 	INTEL_GLK_IDS(IGD_DEVICE, &igd_ops_gen3),
 	INTEL_CNL_IDS(IGD_DEVICE, &igd_ops_gen3),
+	INTEL_ICL_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_EHL_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_JSL_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_TGL_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_RKL_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_ADLS_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_ADLP_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_ADLN_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_RPLS_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_RPLU_IDS(IGD_DEVICE, &igd_ops_gen11),
+	INTEL_RPLP_IDS(IGD_DEVICE, &igd_ops_gen11),
 };
 
 static const struct igd_ops *