git: ddd0d4f4cd65 - main - riscv: Fix SSTC extension support

The branch main has been updated by br:

URL: https://cgit.FreeBSD.org/src/commit/?id=ddd0d4f4cd65341a07bb3bb833dee7982018fd60

commit ddd0d4f4cd65341a07bb3bb833dee7982018fd60
Author:     Ruslan Bukin <br@FreeBSD.org>
AuthorDate: 2024-05-22 14:51:45 +0000
Commit:     Ruslan Bukin <br@FreeBSD.org>
CommitDate: 2024-05-22 15:44:03 +0000

    riscv: Fix SSTC extension support
    
    From the SSTC spec:
    "If the stimecmp (supervisor-mode timer compare) register is implemented,
    then STIP is read-only in mip and reflects the supervisor-level timer
    interrupt signal resulting from stimecmp. This timer interrupt signal
    is cleared by writing stimecmp with a value greater than the current time
    value."
    
    This fixes operation in Spike with sstc extension enabled.
    Example:
      spike --isa RV64IMAFDCH_zicntr_zihpm_sstc
    
    Reviewed by:    mhorne
    Differential Revision:  https://reviews.freebsd.org/D45226
---
 sys/riscv/riscv/timer.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/sys/riscv/riscv/timer.c b/sys/riscv/riscv/timer.c
index 06806872d9fd..456dd463ab2a 100644
--- a/sys/riscv/riscv/timer.c
+++ b/sys/riscv/riscv/timer.c
@@ -1,5 +1,5 @@
 /*-
- * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
+ * Copyright (c) 2015-2024 Ruslan Bukin <br@bsdpad.com>
  * All rights reserved.
  *
  * Portions of this software were developed by SRI International and the
@@ -143,7 +143,10 @@ riscv_timer_intr(void *arg)
 
 	sc = (struct riscv_timer_softc *)arg;
 
-	csr_clear(sip, SIP_STIP);
+	if (has_sstc)
+		csr_write(stimecmp, -1UL);
+	else
+		csr_clear(sip, SIP_STIP);
 
 	if (sc->et.et_active)
 		sc->et.et_event_cb(&sc->et, sc->et.et_arg);