From nobody Wed May 22 08:32:00 2024 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Vkl0J6sgkz5LD09; Wed, 22 May 2024 08:32:00 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Vkl0J4vqRz4jSl; Wed, 22 May 2024 08:32:00 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1716366720; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=IUc/Do33OzDsJRWhcbweIzfOl9y/A/04boeGmVwLyJU=; b=uQV0iq9pYft/C2hu35HUlEaY0cXAOEc7TX/6DMNi0gwt97K5vE942taVLLWJNuY00/k8RE edX5foOXNDxCQiuPguZznwiV+ws7d0tq4ClKld8xRfjwbBRA/fJSiU6AnCX2We3bYfdaZ+ b6MrgewlvEhS5tdYjabinyun2qP1za4Eg3HJ46y+875dP3w8lopMaweP4C2YF8qxduHi2S ZDy9nrVDGMofhKlIOgtBUKn4Dd2i5XZMB9mSW12Npiyr/Mv4h5vI8kHAQqEVsXaW2apbtJ AtE2+PQHuQoX8dDdsBIJYKTEvvb8VxxNVtl4iDr4aQVOm0biJQE9Q1BMLjJS0Q== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1716366720; a=rsa-sha256; cv=none; b=Og6WFSMRpEcwj6gwvE8BbDP/KjA0KOWSg0GqYO8eFGwrYi1gnUXxQnl+Gr2MDuoKSlc+xH W2qf2SeOBPbWezW6oroTUUkK/SmGkZlM/r/R0/Z4zdUZkPFmJworGCuTY6T7pfl3TvmHjc DOQnRGU5xSC6hJHxwtvtsbexnkoLNjrAn7gtMf412jPAy/F0M5eW6iU2M8+IFc+0/SC9iz 6ilGMsmXS6Q/6nbEuiWmohhsiL4ZMHuWzTuYu2Qjr+xft6C3OpEy/mxD9/O6JC/4fIBini /q1bTNEkJ++SC8Xmsm3+xDIlnoRspKnLquVoM2j87/QlVtW1iBCd542kgzzUsA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1716366720; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=IUc/Do33OzDsJRWhcbweIzfOl9y/A/04boeGmVwLyJU=; b=yFbgFmmonKeGkXmYXktSPQjovnN7DsnMa4PVyeCc+FCqPsMs/hONNovcuIIwJQCStGY8rb bezqOmRd1vmfm62kzMtazomS6DoDK7e66cCB0RkHfkMFBDtTwxDCe7S+YwwFvSybjQkEPy LZBLPqlWPFz8iBt27Gvmw0fxjzE5GC5RaCyTZ+apCsLAoljt2dR3R329dhyVPgeyJuRqW0 rvn0Z0FzUbSfaZ/fE4Md5JgsVGKu0d5SMgxILPdnMBgDOb7qAVw/6Lvq/1I6eDo4gsX5r0 leeS8TYMTqujKmwm6+/sylRSFLIiAG8CZfqLL6QpTSANoUWIsxPT5fXCkxxYEA== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4Vkl0J4TjzzyhX; Wed, 22 May 2024 08:32:00 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.17.1/8.17.1) with ESMTP id 44M8W0mW008873; Wed, 22 May 2024 08:32:00 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.17.1/8.17.1/Submit) id 44M8W0T9008870; Wed, 22 May 2024 08:32:00 GMT (envelope-from git) Date: Wed, 22 May 2024 08:32:00 GMT Message-Id: <202405220832.44M8W0T9008870@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: 29c1cf9860e5 - main - arm64: Use the UL macro in TCR_EL1 defines List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 29c1cf9860e531146220d9dc3596e4c79f91cfcd Auto-Submitted: auto-generated The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=29c1cf9860e531146220d9dc3596e4c79f91cfcd commit 29c1cf9860e531146220d9dc3596e4c79f91cfcd Author: Andrew Turner AuthorDate: 2024-05-22 08:18:39 +0000 Commit: Andrew Turner CommitDate: 2024-05-22 08:18:39 +0000 arm64: Use the UL macro in TCR_EL1 defines While clang can handle numbers with a UL suffix in assembly files gcc/gas is unable to. Switch to use the UL macro for TCR_EL1 defines as some are used in locore.S Reviewed by: brooks, jhb Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45261 --- sys/arm64/include/armreg.h | 96 +++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index d1480cd61184..2af207a40009 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -2151,99 +2151,99 @@ /* TCR_EL1 - Translation Control Register */ /* Bits 63:59 are reserved */ #define TCR_TCMA1_SHIFT 58 -#define TCR_TCMA1 (1UL << TCR_TCMA1_SHIFT) +#define TCR_TCMA1 (UL(1) << TCR_TCMA1_SHIFT) #define TCR_TCMA0_SHIFT 57 -#define TCR_TCMA0 (1UL << TCR_TCMA0_SHIFT) +#define TCR_TCMA0 (UL(1) << TCR_TCMA0_SHIFT) #define TCR_E0PD1_SHIFT 56 -#define TCR_E0PD1 (1UL << TCR_E0PD1_SHIFT) +#define TCR_E0PD1 (UL(1) << TCR_E0PD1_SHIFT) #define TCR_E0PD0_SHIFT 55 -#define TCR_E0PD0 (1UL << TCR_E0PD0_SHIFT) +#define TCR_E0PD0 (UL(1) << TCR_E0PD0_SHIFT) #define TCR_NFD1_SHIFT 54 -#define TCR_NFD1 (1UL << TCR_NFD1_SHIFT) +#define TCR_NFD1 (UL(1) << TCR_NFD1_SHIFT) #define TCR_NFD0_SHIFT 53 -#define TCR_NFD0 (1UL << TCR_NFD0_SHIFT) +#define TCR_NFD0 (UL(1) << TCR_NFD0_SHIFT) #define TCR_TBID1_SHIFT 52 -#define TCR_TBID1 (1UL << TCR_TBID1_SHIFT) +#define TCR_TBID1 (UL(1) << TCR_TBID1_SHIFT) #define TCR_TBID0_SHIFT 51 -#define TCR_TBID0 (1UL << TCR_TBID0_SHIFT) +#define TCR_TBID0 (UL(1) << TCR_TBID0_SHIFT) #define TCR_HWU162_SHIFT 50 -#define TCR_HWU162 (1UL << TCR_HWU162_SHIFT) +#define TCR_HWU162 (UL(1) << TCR_HWU162_SHIFT) #define TCR_HWU161_SHIFT 49 -#define TCR_HWU161 (1UL << TCR_HWU161_SHIFT) +#define TCR_HWU161 (UL(1) << TCR_HWU161_SHIFT) #define TCR_HWU160_SHIFT 48 -#define TCR_HWU160 (1UL << TCR_HWU160_SHIFT) +#define TCR_HWU160 (UL(1) << TCR_HWU160_SHIFT) #define TCR_HWU159_SHIFT 47 -#define TCR_HWU159 (1UL << TCR_HWU159_SHIFT) +#define TCR_HWU159 (UL(1) << TCR_HWU159_SHIFT) #define TCR_HWU1 \ (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162) #define TCR_HWU062_SHIFT 46 -#define TCR_HWU062 (1UL << TCR_HWU062_SHIFT) +#define TCR_HWU062 (UL(1) << TCR_HWU062_SHIFT) #define TCR_HWU061_SHIFT 45 -#define TCR_HWU061 (1UL << TCR_HWU061_SHIFT) +#define TCR_HWU061 (UL(1) << TCR_HWU061_SHIFT) #define TCR_HWU060_SHIFT 44 -#define TCR_HWU060 (1UL << TCR_HWU060_SHIFT) +#define TCR_HWU060 (UL(1) << TCR_HWU060_SHIFT) #define TCR_HWU059_SHIFT 43 -#define TCR_HWU059 (1UL << TCR_HWU059_SHIFT) +#define TCR_HWU059 (UL(1) << TCR_HWU059_SHIFT) #define TCR_HWU0 \ (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062) #define TCR_HPD1_SHIFT 42 -#define TCR_HPD1 (1UL << TCR_HPD1_SHIFT) +#define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT) #define TCR_HPD0_SHIFT 41 -#define TCR_HPD0 (1UL << TCR_HPD0_SHIFT) +#define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT) #define TCR_HD_SHIFT 40 -#define TCR_HD (1UL << TCR_HD_SHIFT) +#define TCR_HD (UL(1) << TCR_HD_SHIFT) #define TCR_HA_SHIFT 39 -#define TCR_HA (1UL << TCR_HA_SHIFT) +#define TCR_HA (UL(1) << TCR_HA_SHIFT) #define TCR_TBI1_SHIFT 38 -#define TCR_TBI1 (1UL << TCR_TBI1_SHIFT) +#define TCR_TBI1 (UL(1) << TCR_TBI1_SHIFT) #define TCR_TBI0_SHIFT 37 -#define TCR_TBI0 (1UL << TCR_TBI0_SHIFT) +#define TCR_TBI0 (UL(1) << TCR_TBI0_SHIFT) #define TCR_ASID_SHIFT 36 #define TCR_ASID_WIDTH 1 -#define TCR_ASID_16 (1UL << TCR_ASID_SHIFT) +#define TCR_ASID_16 (UL(1) << TCR_ASID_SHIFT) /* Bit 35 is reserved */ #define TCR_IPS_SHIFT 32 #define TCR_IPS_WIDTH 3 -#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) -#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) -#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) -#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) -#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) -#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) +#define TCR_IPS_32BIT (UL(0) << TCR_IPS_SHIFT) +#define TCR_IPS_36BIT (UL(1) << TCR_IPS_SHIFT) +#define TCR_IPS_40BIT (UL(2) << TCR_IPS_SHIFT) +#define TCR_IPS_42BIT (UL(3) << TCR_IPS_SHIFT) +#define TCR_IPS_44BIT (UL(4) << TCR_IPS_SHIFT) +#define TCR_IPS_48BIT (UL(5) << TCR_IPS_SHIFT) #define TCR_TG1_SHIFT 30 -#define TCR_TG1_MASK (3UL << TCR_TG1_SHIFT) -#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) -#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) -#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) +#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT) +#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT) +#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) +#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) #define TCR_SH1_SHIFT 28 -#define TCR_SH1_IS (3UL << TCR_SH1_SHIFT) +#define TCR_SH1_IS (UL(3) << TCR_SH1_SHIFT) #define TCR_ORGN1_SHIFT 26 -#define TCR_ORGN1_WBWA (1UL << TCR_ORGN1_SHIFT) +#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT) #define TCR_IRGN1_SHIFT 24 -#define TCR_IRGN1_WBWA (1UL << TCR_IRGN1_SHIFT) +#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT) #define TCR_EPD1_SHIFT 23 -#define TCR_EPD1 (1UL << TCR_EPD1_SHIFT) +#define TCR_EPD1 (UL(1) << TCR_EPD1_SHIFT) #define TCR_A1_SHIFT 22 -#define TCR_A1 (0x1UL << TCR_A1_SHIFT) +#define TCR_A1 (UL(1) << TCR_A1_SHIFT) #define TCR_T1SZ_SHIFT 16 -#define TCR_T1SZ_MASK (0x3fUL << TCR_T1SZ_SHIFT) +#define TCR_T1SZ_MASK (UL(0x3f) << TCR_T1SZ_SHIFT) #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) #define TCR_TG0_SHIFT 14 -#define TCR_TG0_MASK (3UL << TCR_TG0_SHIFT) -#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) -#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) -#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) +#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) +#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT) +#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT) +#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT) #define TCR_SH0_SHIFT 12 -#define TCR_SH0_IS (3UL << TCR_SH0_SHIFT) +#define TCR_SH0_IS (UL(3) << TCR_SH0_SHIFT) #define TCR_ORGN0_SHIFT 10 -#define TCR_ORGN0_WBWA (1UL << TCR_ORGN0_SHIFT) +#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT) #define TCR_IRGN0_SHIFT 8 -#define TCR_IRGN0_WBWA (1UL << TCR_IRGN0_SHIFT) +#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT) #define TCR_EPD0_SHIFT 7 -#define TCR_EPD0 (1UL << TCR_EPD0_SHIFT) +#define TCR_EPD0 (UL(1) << TCR_EPD0_SHIFT) /* Bit 6 is reserved */ #define TCR_T0SZ_SHIFT 0 -#define TCR_T0SZ_MASK (0x3fUL << TCR_T0SZ_SHIFT) +#define TCR_T0SZ_MASK (UL(0x3f) << TCR_T0SZ_SHIFT) #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))