git: 35e63136a8c2 - main - rtwn: add a register value for R92C_FPGA0_POWER_SAVE, and other bits

The branch main has been updated by adrian:

URL: https://cgit.FreeBSD.org/src/commit/?id=35e63136a8c264b96cc07c1a2cd51e5894cfa67c

commit 35e63136a8c264b96cc07c1a2cd51e5894cfa67c
Author:     Adrian Chadd <adrian@FreeBSD.org>
AuthorDate: 2024-12-06 23:51:07 +0000
Commit:     Adrian Chadd <adrian@FreeBSD.org>
CommitDate: 2024-12-14 02:17:52 +0000

    rtwn: add a register value for R92C_FPGA0_POWER_SAVE, and other bits
    
    * add a register value for the R92C_FPGA0_POWER_SAVE register
    * add the field names and mask
    * add a mask for the 40MHz upper/lower bits in R92C_RMRR; I think
      I need to debug and overhaul the 20/40MHz config path to get 40MHz
      working right.
    
    Local testing:
    
    * rtl8188eu, sta mode
    * rtl8192cu, sta mode
---
 sys/dev/rtwn/rtl8192c/r92c_chan.c | 3 ++-
 sys/dev/rtwn/rtl8192c/r92c_reg.h  | 7 +++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/sys/dev/rtwn/rtl8192c/r92c_chan.c b/sys/dev/rtwn/rtl8192c/r92c_chan.c
index 55d73c934f1e..108fbbf16c59 100644
--- a/sys/dev/rtwn/rtl8192c/r92c_chan.c
+++ b/sys/dev/rtwn/rtl8192c/r92c_chan.c
@@ -262,7 +262,8 @@ r92c_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo)
 	rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2,
 	    R92C_FPGA0_ANAPARAM2_CBW20, 0);
 
-	rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26);
+	rtwn_bb_setbits(sc, R92C_FPGA0_POWER_SAVE,
+	    R92C_FPGA0_POWER_SAVE_PS_MASK, (prichlo ? 2 : 1) << 26);
 
 	/* Select 40MHz bandwidth. */
 	rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
diff --git a/sys/dev/rtwn/rtl8192c/r92c_reg.h b/sys/dev/rtwn/rtl8192c/r92c_reg.h
index e640b6b560b1..6ca4a4eca031 100644
--- a/sys/dev/rtwn/rtl8192c/r92c_reg.h
+++ b/sys/dev/rtwn/rtl8192c/r92c_reg.h
@@ -520,6 +520,7 @@
 #define R92C_RRSR_RATE_BITMAP_S		0
 #define R92C_RRSR_RATE_CCK_ONLY_1M	0xffff1
 #define R92C_RRSR_RATE_ALL		0xfffff
+#define R92C_RRSR_RSC_SUBCHNL_MASK	0x00600000
 #define R92C_RRSR_RSC_LOWSUBCHNL	0x00200000
 #define R92C_RRSR_RSC_UPSUBCHNL		0x00400000
 #define R92C_RRSR_SHORT			0x00800000
@@ -668,6 +669,7 @@
  */
 #define R92C_FPGA0_RFMOD		0x800
 #define R92C_FPGA0_TXINFO		0x804
+#define R92C_FPGA0_POWER_SAVE		0x818
 #define R92C_HSSI_PARAM1(chain)		(0x820 + (chain) * 8)
 #define R92C_HSSI_PARAM2(chain)		(0x824 + (chain) * 8)
 #define R92C_TXAGC_RATE18_06(i)		(((i) == 0) ? 0xe00 : 0x830)
@@ -725,6 +727,11 @@
 #define R92C_RFMOD_CCK_EN	0x01000000
 #define R92C_RFMOD_OFDM_EN	0x02000000
 
+/* Bits for R92C_FPGA0_POWER_SAVE. */
+#define R92C_FPGA0_POWER_SAVE_PS_MASK		0x0c000000
+#define R92C_FPGA0_POWER_SAVE_PS_LOWER_CHANNEL	0x04000000
+#define R92C_FPGA0_POWER_SAVE_PS_UPPER_CHANNEL	0x08000000
+
 /* Bits for R92C_HSSI_PARAM1(i). */
 #define R92C_HSSI_PARAM1_PI	0x00000100