git: 419f8fc7fbc8 - main - Add more arm64 special registers

The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=419f8fc7fbc8b860df92db58d13ac9c9aafa1c10

commit 419f8fc7fbc8b860df92db58d13ac9c9aafa1c10
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2023-05-04 10:30:57 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2023-05-24 10:55:38 +0000

    Add more arm64 special registers
    
    These will be used by bhyve
    
    Reviewed by:    markj
    Sponsored by:   Arm Ltd
    Sponsored by:   Innovate UK
    Sponsored by:   The FreeBSD Foundation
    Differential Revision:  https://reviews.freebsd.org/D40128
---
 sys/arm64/include/armreg.h | 48 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 45f6145de8bd..5c174bcbc838 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -435,12 +435,24 @@
 #define	ICC_SGI1R_EL1_CRn		12
 #define	ICC_SGI1R_EL1_CRm		11
 #define	ICC_SGI1R_EL1_op2		5
-#define	ICC_SGI1R_EL1_TL_MASK		0xffffUL
+#define	ICC_SGI1R_EL1_TL_SHIFT		0
+#define	ICC_SGI1R_EL1_TL_MASK		(0xffffUL << ICC_SGI1R_EL1_TL_SHIFT)
+#define	ICC_SGI1R_EL1_TL_VAL(x)		((x) & ICC_SGI1R_EL1_TL_MASK)
 #define	ICC_SGI1R_EL1_AFF1_SHIFT	16
+#define	ICC_SGI1R_EL1_AFF1_MASK		(0xfful << ICC_SGI1R_EL1_AFF1_SHIFT)
+#define	ICC_SGI1R_EL1_AFF1_VAL(x)	((x) & ICC_SGI1R_EL1_AFF1_MASK)
 #define	ICC_SGI1R_EL1_SGIID_SHIFT	24
+#define	ICC_SGI1R_EL1_SGIID_MASK	(0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT)
+#define	ICC_SGI1R_EL1_SGIID_VAL(x)	((x) & ICC_SGI1R_EL1_SGIID_MASK)
 #define	ICC_SGI1R_EL1_AFF2_SHIFT	32
+#define	ICC_SGI1R_EL1_AFF2_MASK		(0xfful << ICC_SGI1R_EL1_AFF2_SHIFT)
+#define	ICC_SGI1R_EL1_AFF2_VAL(x)	((x) & ICC_SGI1R_EL1_AFF2_MASK)
+#define	ICC_SGI1R_EL1_RS_SHIFT		44
+#define	ICC_SGI1R_EL1_RS_MASK		(0xful << ICC_SGI1R_EL1_RS_SHIFT)
+#define	ICC_SGI1R_EL1_RS_VAL(x)		((x) & ICC_SGI1R_EL1_RS_MASK)
 #define	ICC_SGI1R_EL1_AFF3_SHIFT	48
-#define	ICC_SGI1R_EL1_SGIID_MASK	0xfUL
+#define	ICC_SGI1R_EL1_AFF3_MASK		(0xfful << ICC_SGI1R_EL1_AFF3_SHIFT)
+#define	ICC_SGI1R_EL1_AFF3_VAL(x)	((x) & ICC_SGI1R_EL1_AFF3_MASK)
 #define	ICC_SGI1R_EL1_IRM		(0x1UL << 40)
 
 /* ICC_SRE_EL1 */
@@ -503,6 +515,14 @@
 #define	 ID_AA64DFR0_TraceFilt_NONE	(UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT)
 #define	 ID_AA64DFR0_TraceFilt_8_4	(UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT)
 
+/* ID_AA64DFR1_EL1 */
+#define	ID_AA64DFR1_EL1			MRS_REG(ID_AA64DFR0_EL1)
+#define	ID_AA64DFR1_EL1_op0		3
+#define	ID_AA64DFR1_EL1_op1		0
+#define	ID_AA64DFR1_EL1_CRn		0
+#define	ID_AA64DFR1_EL1_CRm		5
+#define	ID_AA64DFR1_EL1_op2		1
+
 /* ID_AA64ISAR0_EL1 */
 #define	ID_AA64ISAR0_EL1		MRS_REG(ID_AA64ISAR0_EL1)
 #define	ID_AA64ISAR0_EL1_op0		0x3
@@ -1193,6 +1213,30 @@
 #define	MDSCR_MDE_SHIFT			15
 #define	MDSCR_MDE			(UL(0x1) << MDSCR_MDE_SHIFT)
 
+/* MPIDR_EL1 - Multiprocessor Affinity Register */
+#define	MPIDR_EL1			MRS_REG(MPIDR_EL1)
+#define	MPIDR_EL1_op0			3
+#define	MPIDR_EL1_op1			0
+#define	MPIDR_EL1_CRn			0
+#define	MPIDR_EL1_CRm			0
+#define	MPIDR_EL1_op2			5
+#define	MPIDR_AFF0_SHIFT		0
+#define	MPIDR_AFF0_MASK			(UL(0xff) << MPIDR_AFF0_SHIFT)
+#define	MPIDR_AFF0_VAL(x)		((x) & MPIDR_AFF0_MASK)
+#define	MPIDR_AFF1_SHIFT		8
+#define	MPIDR_AFF1_MASK			(UL(0xff) << MPIDR_AFF1_SHIFT)
+#define	MPIDR_AFF1_VAL(x)		((x) & MPIDR_AFF1_MASK)
+#define	MPIDR_AFF2_SHIFT		16
+#define	MPIDR_AFF2_MASK			(UL(0xff) << MPIDR_AFF2_SHIFT)
+#define	MPIDR_AFF2_VAL(x)		((x) & MPIDR_AFF2_MASK)
+#define	MPIDR_MT_SHIFT			24
+#define	MPIDR_MT_MASK			(UL(0x1) << MPIDR_MT_SHIFT)
+#define	MPIDR_U_SHIFT			30
+#define	MPIDR_U_MASK			(UL(0x1) << MPIDR_U_SHIFT)
+#define	MPIDR_AFF3_SHIFT		32
+#define	MPIDR_AFF3_MASK			(UL(0xff) << MPIDR_AFF3_SHIFT)
+#define	MPIDR_AFF3_VAL(x)		((x) & MPIDR_AFF3_MASK)
+
 /* MVFR0_EL1 */
 #define	MVFR0_EL1			MRS_REG(MVFR0_EL1)
 #define	MVFR0_EL1_op0			0x3