git: 6fd44e5f5309 - main - arm64: Update the ID_AA64DFR0_EL1 fields

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From: Andrew Turner <andrew_at_FreeBSD.org>
Date: Fri, 28 Jul 2023 12:07:59 UTC
The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=6fd44e5f530935a26f58637594ac22719324fb12

commit 6fd44e5f530935a26f58637594ac22719324fb12
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2023-03-13 09:17:32 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2023-07-28 11:53:01 +0000

    arm64: Update the ID_AA64DFR0_EL1 fields
    
    While here move to decimal for the _op and _CR definitions to be used
    by a future macro to define the register when the assembler doesn't
    know about it.
    
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D40887
---
 sys/arm64/arm64/identcpu.c | 44 ++++++++++++++++++++++++++++++++++++++------
 sys/arm64/include/armreg.h | 44 ++++++++++++++++++++++++++++++++++++++------
 2 files changed, 76 insertions(+), 12 deletions(-)

diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
index bbb3e2d1484b..fc75eec05129 100644
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -365,6 +365,28 @@ static const struct mrs_field id_aa64afr1_fields[] = {
 
 
 /* ID_AA64DFR0_EL1 */
+static const struct mrs_field_value id_aa64dfr0_hpmn0[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, HPMN0, CONSTR, DEFINED),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64dfr0_brbe[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, BRBE, NONE, IMPL),
+	MRS_FIELD_VALUE(ID_AA64DFR0_BRBE_EL3, "BRBE EL3"),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64dfr0_mtpmu[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, MTPMU, NONE, IMPL),
+	MRS_FIELD_VALUE(ID_AA64DFR0_MTPMU_NONE_MT_RES0, "MTPMU res0"),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64dfr0_tracebuffer[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, TraceBuffer, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
 static const struct mrs_field_value id_aa64dfr0_tracefilt[] = {
 	MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_NONE, ""),
 	MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_8_4, "Trace v8.4"),
@@ -380,7 +402,9 @@ static const struct mrs_field_value id_aa64dfr0_doublelock[] = {
 static const struct mrs_field_value id_aa64dfr0_pmsver[] = {
 	MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_NONE, ""),
 	MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE, "SPE"),
-	MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_8_3, "SPE v8.3"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_1, "SPEv1p1"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_2, "SPEv1p2"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_3, "SPEv1p3"),
 	MRS_FIELD_VALUE_END,
 };
 
@@ -402,9 +426,11 @@ static const struct mrs_field_value id_aa64dfr0_brps[] = {
 static const struct mrs_field_value id_aa64dfr0_pmuver[] = {
 	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_NONE, ""),
 	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3, "PMUv3"),
-	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3 v8.1"),
-	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_4, "PMUv3 v8.4"),
-	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_5, "PMUv3 v8.5"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3p1"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_4, "PMUv3p4"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_5, "PMUv3p5"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_7, "PMUv3p7"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_8, "PMUv3p8"),
 	MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_IMPL, "IMPL PMU"),
 	MRS_FIELD_VALUE_END,
 };
@@ -418,12 +444,18 @@ static const struct mrs_field_value id_aa64dfr0_tracever[] = {
 static const struct mrs_field_value id_aa64dfr0_debugver[] = {
 	MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8, "Debugv8"),
 	MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_VHE, "Debugv8_VHE"),
-	MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_2, "Debugv8.2"),
-	MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_4, "Debugv8.4"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_2, "Debugv8p2"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_4, "Debugv8p4"),
+	MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_8, "Debugv8p8"),
 	MRS_FIELD_VALUE_END,
 };
 
 static const struct mrs_field id_aa64dfr0_fields[] = {
+	MRS_FIELD(ID_AA64DFR0, HPMN0, false, MRS_EXACT, id_aa64dfr0_hpmn0),
+	MRS_FIELD(ID_AA64DFR0, BRBE, false, MRS_EXACT, id_aa64dfr0_brbe),
+	MRS_FIELD(ID_AA64DFR0, MTPMU, true, MRS_EXACT, id_aa64dfr0_mtpmu),
+	MRS_FIELD(ID_AA64DFR0, TraceBuffer, false, MRS_EXACT,
+	    id_aa64dfr0_tracebuffer),
 	MRS_FIELD(ID_AA64DFR0, TraceFilt, false, MRS_EXACT,
 	    id_aa64dfr0_tracefilt),
 	MRS_FIELD(ID_AA64DFR0, DoubleLock, false, MRS_EXACT,
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index f20b7a8c710e..15346bcce8ab 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -473,11 +473,11 @@
 
 /* ID_AA64DFR0_EL1 */
 #define	ID_AA64DFR0_EL1			MRS_REG(ID_AA64DFR0_EL1)
-#define	ID_AA64DFR0_EL1_op0		0x3
-#define	ID_AA64DFR0_EL1_op1		0x0
-#define	ID_AA64DFR0_EL1_CRn		0x0
-#define	ID_AA64DFR0_EL1_CRm		0x5
-#define	ID_AA64DFR0_EL1_op2		0x0
+#define	ID_AA64DFR0_EL1_op0		3
+#define	ID_AA64DFR0_EL1_op1		0
+#define	ID_AA64DFR0_EL1_CRn		0
+#define	ID_AA64DFR0_EL1_CRm		5
+#define	ID_AA64DFR0_EL1_op2		0
 #define	ID_AA64DFR0_DebugVer_SHIFT	0
 #define	ID_AA64DFR0_DebugVer_MASK	(UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
 #define	ID_AA64DFR0_DebugVer_VAL(x)	((x) & ID_AA64DFR0_DebugVer_MASK)
@@ -485,6 +485,7 @@
 #define	 ID_AA64DFR0_DebugVer_8_VHE	(UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
 #define	 ID_AA64DFR0_DebugVer_8_2	(UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
 #define	 ID_AA64DFR0_DebugVer_8_4	(UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT)
+#define	 ID_AA64DFR0_DebugVer_8_8	(UL(0xa) << ID_AA64DFR0_DebugVer_SHIFT)
 #define	ID_AA64DFR0_TraceVer_SHIFT	4
 #define	ID_AA64DFR0_TraceVer_MASK	(UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
 #define	ID_AA64DFR0_TraceVer_VAL(x)	((x) & ID_AA64DFR0_TraceVer_MASK)
@@ -498,11 +499,18 @@
 #define	 ID_AA64DFR0_PMUVer_3_1		(UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
 #define	 ID_AA64DFR0_PMUVer_3_4		(UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT)
 #define	 ID_AA64DFR0_PMUVer_3_5		(UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT)
+#define	 ID_AA64DFR0_PMUVer_3_7		(UL(0x7) << ID_AA64DFR0_PMUVer_SHIFT)
+#define	 ID_AA64DFR0_PMUVer_3_8		(UL(0x8) << ID_AA64DFR0_PMUVer_SHIFT)
 #define	 ID_AA64DFR0_PMUVer_IMPL	(UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 #define	ID_AA64DFR0_BRPs_SHIFT		12
 #define	ID_AA64DFR0_BRPs_MASK		(UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
 #define	ID_AA64DFR0_BRPs_VAL(x)	\
     ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
+#define	ID_AA64DFR0_PMSS_SHIFT		16
+#define	ID_AA64DFR0_PMSS_MASK		(UL(0xf) << ID_AA64DFR0_PMSS_SHIFT)
+#define	ID_AA64DFR0_PMSS_VAL(x)		((x) & ID_AA64DFR0_PMSS_MASK)
+#define	 ID_AA64DFR0_PMSS_NONE		(UL(0x0) << ID_AA64DFR0_PMSS_SHIFT)
+#define	 ID_AA64DFR0_PMSS_IMPL		(UL(0x1) << ID_AA64DFR0_PMSS_SHIFT)
 #define	ID_AA64DFR0_WRPs_SHIFT		20
 #define	ID_AA64DFR0_WRPs_MASK		(UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
 #define	ID_AA64DFR0_WRPs_VAL(x)	\
@@ -516,7 +524,9 @@
 #define	ID_AA64DFR0_PMSVer_VAL(x)	((x) & ID_AA64DFR0_PMSVer_MASK)
 #define	 ID_AA64DFR0_PMSVer_NONE	(UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
 #define	 ID_AA64DFR0_PMSVer_SPE		(UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
-#define	 ID_AA64DFR0_PMSVer_SPE_8_3	(UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT)
+#define	 ID_AA64DFR0_PMSVer_SPE_1_1	(UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT)
+#define	 ID_AA64DFR0_PMSVer_SPE_1_2	(UL(0x3) << ID_AA64DFR0_PMSVer_SHIFT)
+#define	 ID_AA64DFR0_PMSVer_SPE_1_3	(UL(0x4) << ID_AA64DFR0_PMSVer_SHIFT)
 #define	ID_AA64DFR0_DoubleLock_SHIFT	36
 #define	ID_AA64DFR0_DoubleLock_MASK	(UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
 #define	ID_AA64DFR0_DoubleLock_VAL(x)	((x) & ID_AA64DFR0_DoubleLock_MASK)
@@ -527,6 +537,28 @@
 #define	ID_AA64DFR0_TraceFilt_VAL(x)	((x) & ID_AA64DFR0_TraceFilt_MASK)
 #define	 ID_AA64DFR0_TraceFilt_NONE	(UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT)
 #define	 ID_AA64DFR0_TraceFilt_8_4	(UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT)
+#define	ID_AA64DFR0_TraceBuffer_SHIFT	44
+#define	ID_AA64DFR0_TraceBuffer_MASK	(UL(0xf) << ID_AA64DFR0_TraceBuffer_SHIFT)
+#define	ID_AA64DFR0_TraceBuffer_VAL(x)	((x) & ID_AA64DFR0_TraceBuffer_MASK)
+#define	 ID_AA64DFR0_TraceBuffer_NONE	(UL(0x0) << ID_AA64DFR0_TraceBuffer_SHIFT)
+#define	 ID_AA64DFR0_TraceBuffer_IMPL	(UL(0x1) << ID_AA64DFR0_TraceBuffer_SHIFT)
+#define	ID_AA64DFR0_MTPMU_SHIFT		48
+#define	ID_AA64DFR0_MTPMU_MASK		(UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT)
+#define	ID_AA64DFR0_MTPMU_VAL(x)	((x) & ID_AA64DFR0_MTPMU_MASK)
+#define	 ID_AA64DFR0_MTPMU_NONE		(UL(0x0) << ID_AA64DFR0_MTPMU_SHIFT)
+#define	 ID_AA64DFR0_MTPMU_IMPL		(UL(0x1) << ID_AA64DFR0_MTPMU_SHIFT)
+#define	 ID_AA64DFR0_MTPMU_NONE_MT_RES0	(UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT)
+#define	ID_AA64DFR0_BRBE_SHIFT		52
+#define	ID_AA64DFR0_BRBE_MASK		(UL(0xf) << ID_AA64DFR0_BRBE_SHIFT)
+#define	ID_AA64DFR0_BRBE_VAL(x)		((x) & ID_AA64DFR0_BRBE_MASK)
+#define	 ID_AA64DFR0_BRBE_NONE		(UL(0x0) << ID_AA64DFR0_BRBE_SHIFT)
+#define	 ID_AA64DFR0_BRBE_IMPL		(UL(0x1) << ID_AA64DFR0_BRBE_SHIFT)
+#define	 ID_AA64DFR0_BRBE_EL3		(UL(0x2) << ID_AA64DFR0_BRBE_SHIFT)
+#define	ID_AA64DFR0_HPMN0_SHIFT		60
+#define	ID_AA64DFR0_HPMN0_MASK		(UL(0xf) << ID_AA64DFR0_HPMN0_SHIFT)
+#define	ID_AA64DFR0_HPMN0_VAL(x)	((x) & ID_AA64DFR0_HPMN0_MASK)
+#define	 ID_AA64DFR0_HPMN0_CONSTR	(UL(0x0) << ID_AA64DFR0_HPMN0_SHIFT)
+#define	 ID_AA64DFR0_HPMN0_DEFINED	(UL(0x1) << ID_AA64DFR0_HPMN0_SHIFT)
 
 /* ID_AA64DFR1_EL1 */
 #define	ID_AA64DFR1_EL1			MRS_REG(ID_AA64DFR1_EL1)