git: 47cf1b37f42d - main - vmm: Expose some more AVX512 CPUID bits to guests

The branch main has been updated by markj:

URL: https://cgit.FreeBSD.org/src/commit/?id=47cf1b37f42d2acb24fa3a1e6106374dddb3edbf

commit 47cf1b37f42d2acb24fa3a1e6106374dddb3edbf
Author:     Mark Johnston <markj@FreeBSD.org>
AuthorDate: 2023-04-25 17:33:08 +0000
Commit:     Mark Johnston <markj@FreeBSD.org>
CommitDate: 2023-04-25 17:35:14 +0000

    vmm: Expose some more AVX512 CPUID bits to guests
    
    This is required to announce support for some accelerated AES
    operations.  AVX512BW indicates support for the AVX512-FP16 extension
    and AVX512VL indicates support for the use of AVX512 instructions with
    vector lengths smaller than 512 bits.
    
    VAES and VPCLMULQDQ extensions indicate that VEX-prefixed AES-NI and
    pclmulqdq instructions are supported.
    
    All of these bits are needed for OpenSSL to use VAES to accelerate
    AES-GCM transforms.
    
    Reviewed by:    corvink, kib, jhb
    MFC after:      2 weeks
    Sponsored by:   Stormshield
    Sponsored by:   Klara, Inc.
    Differential Revision:  https://reviews.freebsd.org/D39781
---
 sys/amd64/vmm/x86.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/sys/amd64/vmm/x86.c b/sys/amd64/vmm/x86.c
index 2d1b2385d1e8..a054b99c6481 100644
--- a/sys/amd64/vmm/x86.c
+++ b/sys/amd64/vmm/x86.c
@@ -431,18 +431,22 @@ x86_emulate_cpuid(struct vcpu *vcpu, uint64_t *rax, uint64_t *rbx,
 				/*
 				 * Expose known-safe features.
 				 */
-				regs[1] &= (CPUID_STDEXT_FSGSBASE |
+				regs[1] &= CPUID_STDEXT_FSGSBASE |
 				    CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
 				    CPUID_STDEXT_AVX2 | CPUID_STDEXT_SMEP |
 				    CPUID_STDEXT_BMI2 |
 				    CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
 				    CPUID_STDEXT_AVX512F |
+				    CPUID_STDEXT_AVX512DQ |
 				    CPUID_STDEXT_RDSEED |
 				    CPUID_STDEXT_SMAP |
 				    CPUID_STDEXT_AVX512PF |
 				    CPUID_STDEXT_AVX512ER |
-				    CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA);
-				regs[2] = 0;
+				    CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA |
+				    CPUID_STDEXT_AVX512BW |
+				    CPUID_STDEXT_AVX512VL;
+				regs[2] &= CPUID_STDEXT2_VAES |
+				    CPUID_STDEXT2_VPCLMULQDQ;
 				regs[3] &= CPUID_STDEXT3_MD_CLEAR;
 
 				/* Advertise RDPID if it is enabled. */