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Tue, 6 Sep 2022 15:49:53 GMT (envelope-from git) Date: Tue, 6 Sep 2022 15:49:53 GMT Message-Id: <202209061549.286Fnr7A059154@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: a8fac0ce7854 - main - Decode the arm64 ID_AA64ISAR1_EL1 register List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-main@freebsd.org X-BeenThere: dev-commits-src-main@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: a8fac0ce78542781cf2ac7e97569416ec0e795a4 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1662479393; 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mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=a8fac0ce78542781cf2ac7e97569416ec0e795a4 commit a8fac0ce78542781cf2ac7e97569416ec0e795a4 Author: Andrew Turner AuthorDate: 2022-06-28 13:39:03 +0000 Commit: Andrew Turner CommitDate: 2022-09-06 15:49:36 +0000 Decode the arm64 ID_AA64ISAR1_EL1 register Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D35627 --- sys/arm64/arm64/identcpu.c | 83 ++++++++++++++++++++++++++++++++++++++++++++-- sys/arm64/include/armreg.h | 47 ++++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 3 deletions(-) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index ba8da5d48fee..24b1bd0b1dfd 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -127,6 +127,7 @@ struct cpu_desc { uint64_t id_aa64dfr1; uint64_t id_aa64isar0; uint64_t id_aa64isar1; + uint64_t id_aa64isar2; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; @@ -154,6 +155,7 @@ static u_int cpu_print_regs; #define PRINT_ID_AA64_DFR1 0x00000020 #define PRINT_ID_AA64_ISAR0 0x00000100 #define PRINT_ID_AA64_ISAR1 0x00000200 +#define PRINT_ID_AA64_ISAR2 0x00000400 #define PRINT_ID_AA64_MMFR0 0x00001000 #define PRINT_ID_AA64_MMFR1 0x00002000 #define PRINT_ID_AA64_MMFR2 0x00004000 @@ -743,10 +745,10 @@ static struct mrs_field_value id_aa64isar1_apa[] = { MRS_FIELD_VALUE(ID_AA64ISAR1_APA_NONE, ""), MRS_FIELD_VALUE(ID_AA64ISAR1_APA_PAC, "APA PAC"), MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC, "APA EPAC"), - MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "PAuth+EPAC2"), - MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "PAuth+FPAC"), + MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "APA EPAC2"), + MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "APA FPAC"), MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC_COMBINED, - "PAuth+FPAC+Combined"), + "APA FPAC+Combined"), MRS_FIELD_VALUE_END, }; @@ -801,6 +803,73 @@ static struct mrs_field id_aa64isar1_fields[] = { }; +/* ID_AA64ISAR2_EL1 */ +static struct mrs_field_value id_aa64isar2_pac_frac[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, PAC_frac, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64isar2_bc[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, BC, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64isar2_mops[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, MOPS, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64isar2_apa3[] = { + MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_NONE, ""), + MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_PAC, "APA3 PAC"), + MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC, "APA3 EPAC"), + MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC2, "APA3 EPAC2"), + MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC, "APA3 FPAC"), + MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC_COMBINED, + "APA3 FPAC+Combined"), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_hwcap id_aa64isar2_apa3_caps[] = { + MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR2_APA3_PAC), + MRS_HWCAP_END +}; + +static struct mrs_field_value id_aa64isar2_gpa3[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, GPA3, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_hwcap id_aa64isar2_gpa3_caps[] = { + MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR2_GPA3_IMPL), + MRS_HWCAP_END +}; + +static struct mrs_field_value id_aa64isar2_rpres[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, RPRES, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64isar2_wfxt[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, WFxT, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field id_aa64isar2_fields[] = { + MRS_FIELD(ID_AA64ISAR2, PAC_frac, false, MRS_EXACT, + id_aa64isar2_pac_frac), + MRS_FIELD(ID_AA64ISAR2, BC, false, MRS_EXACT, id_aa64isar2_bc), + MRS_FIELD(ID_AA64ISAR2, MOPS, false, MRS_EXACT, id_aa64isar2_mops), + MRS_FIELD_HWCAP(ID_AA64ISAR2, APA3, false, MRS_EXACT, + id_aa64isar2_apa3, id_aa64isar2_apa3_caps), + MRS_FIELD_HWCAP(ID_AA64ISAR2, GPA3, false, MRS_EXACT, + id_aa64isar2_gpa3, id_aa64isar2_gpa3_caps), + MRS_FIELD(ID_AA64ISAR2, RPRES, false, MRS_EXACT, id_aa64isar2_rpres), + MRS_FIELD(ID_AA64ISAR2, WFxT, false, MRS_EXACT, id_aa64isar2_wfxt), + MRS_FIELD_END, +}; + + /* ID_AA64MMFR0_EL1 */ static struct mrs_field_value id_aa64mmfr0_exs[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL), @@ -2179,6 +2248,11 @@ print_cpu_features(u_int cpu) print_id_register(sb, "Instruction Set Attributes 1", cpu_desc[cpu].id_aa64isar1, id_aa64isar1_fields); + /* AArch64 Instruction Set Attribute Register 2 */ + if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR2) != 0) + print_id_register(sb, "Instruction Set Attributes 2", + cpu_desc[cpu].id_aa64isar2, id_aa64isar2_fields); + /* AArch64 Processor Feature Register 0 */ if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR0) != 0) print_id_register(sb, "Processor Features 0", @@ -2308,6 +2382,7 @@ identify_cpu(u_int cpu) cpu_desc[cpu].id_aa64dfr1 = READ_SPECIALREG(id_aa64dfr1_el1); cpu_desc[cpu].id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1); cpu_desc[cpu].id_aa64isar1 = READ_SPECIALREG(id_aa64isar1_el1); + cpu_desc[cpu].id_aa64isar2 = READ_SPECIALREG(id_aa64isar2_el1); cpu_desc[cpu].id_aa64mmfr0 = READ_SPECIALREG(id_aa64mmfr0_el1); cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1); cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1); @@ -2394,6 +2469,8 @@ check_cpu_regs(u_int cpu) cpu_print_regs |= PRINT_ID_AA64_ISAR0; if (cpu_desc[cpu].id_aa64isar1 != cpu_desc[0].id_aa64isar1) cpu_print_regs |= PRINT_ID_AA64_ISAR1; + if (cpu_desc[cpu].id_aa64isar2 != cpu_desc[0].id_aa64isar2) + cpu_print_regs |= PRINT_ID_AA64_ISAR2; if (cpu_desc[cpu].id_aa64mmfr0 != cpu_desc[0].id_aa64mmfr0) cpu_print_regs |= PRINT_ID_AA64_MMFR0; diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 29be4a0276e6..b24c6ec94c65 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -673,6 +673,53 @@ #define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) #define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) +/* ID_AA64ISAR2_EL1 */ +#define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1) +#define ID_AA64ISAR2_EL1_op0 3 +#define ID_AA64ISAR2_EL1_op1 0 +#define ID_AA64ISAR2_EL1_CRn 0 +#define ID_AA64ISAR2_EL1_CRm 6 +#define ID_AA64ISAR2_EL1_op2 2 +#define ID_AA64ISAR2_WFxT_SHIFT 0 +#define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT) +#define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK) +#define ID_AA64ISAR2_WFxT_NONE (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT) +#define ID_AA64ISAR2_WFxT_IMPL (UL(0x1) << ID_AA64ISAR2_WFxT_SHIFT) +#define ID_AA64ISAR2_RPRES_SHIFT 4 +#define ID_AA64ISAR2_RPRES_MASK (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT) +#define ID_AA64ISAR2_RPRES_VAL(x) ((x) & ID_AA64ISAR2_RPRES_MASK) +#define ID_AA64ISAR2_RPRES_NONE (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT) +#define ID_AA64ISAR2_RPRES_IMPL (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT) +#define ID_AA64ISAR2_GPA3_SHIFT 8 +#define ID_AA64ISAR2_GPA3_MASK (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT) +#define ID_AA64ISAR2_GPA3_VAL(x) ((x) & ID_AA64ISAR2_GPA3_MASK) +#define ID_AA64ISAR2_GPA3_NONE (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT) +#define ID_AA64ISAR2_GPA3_IMPL (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT) +#define ID_AA64ISAR2_APA3_SHIFT 12 +#define ID_AA64ISAR2_APA3_MASK (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT) +#define ID_AA64ISAR2_APA3_VAL(x) ((x) & ID_AA64ISAR2_APA3_MASK) +#define ID_AA64ISAR2_APA3_NONE (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT) +#define ID_AA64ISAR2_APA3_PAC (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT) +#define ID_AA64ISAR2_APA3_EPAC (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT) +#define ID_AA64ISAR2_APA3_EPAC2 (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT) +#define ID_AA64ISAR2_APA3_FPAC (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT) +#define ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT) +#define ID_AA64ISAR2_MOPS_SHIFT 16 +#define ID_AA64ISAR2_MOPS_MASK (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT) +#define ID_AA64ISAR2_MOPS_VAL(x) ((x) & ID_AA64ISAR2_MOPS_MASK) +#define ID_AA64ISAR2_MOPS_NONE (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT) +#define ID_AA64ISAR2_MOPS_IMPL (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT) +#define ID_AA64ISAR2_BC_SHIFT 20 +#define ID_AA64ISAR2_BC_MASK (UL(0xf) << ID_AA64ISAR2_BC_SHIFT) +#define ID_AA64ISAR2_BC_VAL(x) ((x) & ID_AA64ISAR2_BC_MASK) +#define ID_AA64ISAR2_BC_NONE (UL(0x0) << ID_AA64ISAR2_BC_SHIFT) +#define ID_AA64ISAR2_BC_IMPL (UL(0x1) << ID_AA64ISAR2_BC_SHIFT) +#define ID_AA64ISAR2_PAC_frac_SHIFT 28 +#define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT) +#define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK) +#define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT) +#define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT) + /* ID_AA64MMFR0_EL1 */ #define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) #define ID_AA64MMFR0_EL1_op0 0x3