git: f4f56ff43dbd - main - qat: Rename to qat_c2xxx and remove support for modern chipsets
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Date: Wed, 27 Jul 2022 15:14:04 UTC
The branch main has been updated by markj:
URL: https://cgit.FreeBSD.org/src/commit/?id=f4f56ff43dbd30930f4b018e39ba2b9abf84551f
commit f4f56ff43dbd30930f4b018e39ba2b9abf84551f
Author: Mark Johnston <markj@FreeBSD.org>
AuthorDate: 2022-07-27 14:55:40 +0000
Commit: Mark Johnston <markj@FreeBSD.org>
CommitDate: 2022-07-27 15:10:52 +0000
qat: Rename to qat_c2xxx and remove support for modern chipsets
A replacement QAT driver will be imported, but this replacement does not
support Atom C2xxx hardware. So, the existing driver will be kept
around to provide opencrypto offload support for those chipsets.
Reviewed by: pauamma, emaste
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D35817
---
share/man/man4/Makefile | 4 +-
share/man/man4/{qat.4 => qat_c2xxx.4} | 26 +-
sys/amd64/conf/NOTES | 6 +-
sys/conf/files.x86 | 13 +-
sys/contrib/dev/qat/qat_895xcc.bin | Bin 813280 -> 0 bytes
sys/contrib/dev/qat/qat_895xcc_mmp.bin | Bin 114176 -> 0 bytes
sys/contrib/dev/qat/qat_c3xxx.bin | Bin 531100 -> 0 bytes
sys/contrib/dev/qat/qat_c3xxx_mmp.bin | Bin 120964 -> 0 bytes
sys/contrib/dev/qat/qat_c62x.bin | Bin 796500 -> 0 bytes
sys/contrib/dev/qat/qat_c62x_mmp.bin | Bin 121604 -> 0 bytes
sys/contrib/dev/qat/qat_d15xx.bin | Bin 796500 -> 0 bytes
sys/contrib/dev/qat/qat_d15xx_mmp.bin | Bin 120964 -> 0 bytes
sys/dev/qat/qat_c3xxx.c | 298 ----
sys/dev/qat/qat_c3xxxreg.h | 178 ---
sys/dev/qat/qat_c62x.c | 314 ----
sys/dev/qat/qat_c62xreg.h | 201 ---
sys/dev/qat/qat_d15xx.c | 314 ----
sys/dev/qat/qat_d15xxreg.h | 201 ---
sys/dev/qat/qat_dh895xcc.c | 271 ----
sys/dev/qat/qat_dh895xccreg.h | 119 --
sys/dev/qat/qat_hw17.c | 674 --------
sys/dev/qat/qat_hw17reg.h | 2460 -----------------------------
sys/dev/qat/qat_hw17var.h | 80 -
sys/dev/{qat => qat_c2xxx}/qat.c | 34 +-
sys/dev/{qat => qat_c2xxx}/qat_ae.c | 0
sys/dev/{qat => qat_c2xxx}/qat_aevar.h | 0
sys/dev/{qat => qat_c2xxx}/qat_c2xxx.c | 0
sys/dev/{qat => qat_c2xxx}/qat_c2xxxreg.h | 0
sys/dev/{qat => qat_c2xxx}/qat_hw15.c | 0
sys/dev/{qat => qat_c2xxx}/qat_hw15reg.h | 0
sys/dev/{qat => qat_c2xxx}/qat_hw15var.h | 0
sys/dev/{qat => qat_c2xxx}/qatreg.h | 0
sys/dev/{qat => qat_c2xxx}/qatvar.h | 0
sys/modules/Makefile | 4 +-
sys/modules/{qat => qat_c2xxx}/Makefile | 11 +-
sys/modules/qatfw/Makefile | 6 +-
sys/modules/qatfw/qat_c3xxx/Makefile | 11 -
sys/modules/qatfw/qat_c62x/Makefile | 11 -
sys/modules/qatfw/qat_d15xx/Makefile | 11 -
sys/modules/qatfw/qat_dh895xcc/Makefile | 11 -
40 files changed, 30 insertions(+), 5228 deletions(-)
diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile
index 4a7f323e2c5c..192bab4155a2 100644
--- a/share/man/man4/Makefile
+++ b/share/man/man4/Makefile
@@ -452,7 +452,7 @@ MAN= aac.4 \
pty.4 \
puc.4 \
pwmc.4 \
- ${_qat.4} \
+ ${_qat_c2xxx.4} \
${_qlxge.4} \
${_qlxgb.4} \
${_qlxgbe.4} \
@@ -830,7 +830,7 @@ _nvme.4= nvme.4
_nvram.4= nvram.4
_padlock.4= padlock.4
_pchtherm.4= pchtherm.4
-_qat.4= qat.4
+_qat_c2xxx.4= qat_c2xxx.4
_rr232x.4= rr232x.4
_speaker.4= speaker.4
_spkr.4= spkr.4
diff --git a/share/man/man4/qat.4 b/share/man/man4/qat_c2xxx.4
similarity index 82%
rename from share/man/man4/qat.4
rename to share/man/man4/qat_c2xxx.4
index bd021304dc4d..6f831fe94712 100644
--- a/share/man/man4/qat.4
+++ b/share/man/man4/qat_c2xxx.4
@@ -24,12 +24,12 @@
.\"
.\" $FreeBSD$
.\"
-.Dd May 7, 2021
-.Dt QAT 4
+.Dd July 21, 2022
+.Dt QAT_C2XXX 4
.Os
.Sh NAME
-.Nm qat
-.Nd Intel QuickAssist Technology (QAT) driver
+.Nm qat_c2xxx
+.Nd Intel QuickAssist Technology (QAT) driver for Atom C2000 chipsets
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
@@ -44,12 +44,8 @@ Alternatively, to load the driver as a
module at boot time, place the following lines in
.Xr loader.conf 5 :
.Bd -literal -offset indent
-qat_load="YES"
+qat_c2xxx_load="YES"
qat_c2xxxfw_load="YES"
-qat_c3xxxfw_load="YES"
-qat_c62xfw_load="YES"
-qat_d15xxfw_load="YES"
-qat_dh895xccfw_load="YES"
.Ed
.Sh DESCRIPTION
The
@@ -57,20 +53,15 @@ The
driver implements
.Xr crypto 4
support for some of the cryptographic acceleration functions of the Intel
-QuickAssist (QAT) device.
-The
-.Nm
-driver supports the QAT devices integrated with Atom C2000 and C3000 and Xeon
-C620 and D-1500 platforms, and the Intel QAT Adapter 8950.
-Other platforms and adapters not listed here may also be supported.
+QuickAssist (QAT) device found on Atom C2000 devices.
QAT devices are enumerated through PCIe and are thus visible in
.Xr pciconf 8
output.
.Pp
The
.Nm
-driver can accelerate AES in CBC, CTR, XTS (except for the C2000) and GCM modes,
-and can perform authenticated encryption combining the CBC, CTR and XTS modes
+driver can accelerate AES in CBC, CTR, and GCM modes,
+and can perform authenticated encryption combining the CBC, and CTR modes
with SHA1-HMAC and SHA2-HMAC.
The
.Nm
@@ -84,6 +75,7 @@ requests that do not satisfy this constraint.
.Xr crypto 4 ,
.Xr ipsec 4 ,
.Xr pci 4 ,
+.Xr qat 4 ,
.Xr random 4 ,
.Xr crypto 7 ,
.Xr crypto 9
diff --git a/sys/amd64/conf/NOTES b/sys/amd64/conf/NOTES
index cf284ec8e5f0..ba6e99c0f8eb 100644
--- a/sys/amd64/conf/NOTES
+++ b/sys/amd64/conf/NOTES
@@ -467,8 +467,10 @@ device vmd
device pmspcv
#
-# Intel QuickAssist
-device qat
+# Intel QuickAssist driver with OpenCrypto support
+#
+# Only for legacy Atom C2XXX chipsets.
+device qat_c2xxx
#
# SafeNet crypto driver: can be moved to the MI NOTES as soon as
diff --git a/sys/conf/files.x86 b/sys/conf/files.x86
index 2866c5617593..a78570a423c9 100644
--- a/sys/conf/files.x86
+++ b/sys/conf/files.x86
@@ -288,15 +288,10 @@ dev/mana/mana_sysctl.c optional mana
dev/mana/shm_channel.c optional mana
dev/mana/hw_channel.c optional mana
dev/mana/gdma_util.c optional mana
-dev/qat/qat.c optional qat
-dev/qat/qat_ae.c optional qat
-dev/qat/qat_c2xxx.c optional qat
-dev/qat/qat_c3xxx.c optional qat
-dev/qat/qat_c62x.c optional qat
-dev/qat/qat_d15xx.c optional qat
-dev/qat/qat_dh895xcc.c optional qat
-dev/qat/qat_hw15.c optional qat
-dev/qat/qat_hw17.c optional qat
+dev/qat_c2xxx/qat.c optional qat_c2xxx
+dev/qat_c2xxx/qat_ae.c optional qat_c2xxx
+dev/qat_c2xxx/qat_c2xxx.c optional qat_c2xxx
+dev/qat_c2xxx/qat_hw15.c optional qat_c2xxx
libkern/x86/crc32_sse42.c standard
#
# x86 shared code between IA32 and AMD64 architectures
diff --git a/sys/contrib/dev/qat/qat_895xcc.bin b/sys/contrib/dev/qat/qat_895xcc.bin
deleted file mode 100644
index 5433dcc8408b..000000000000
Binary files a/sys/contrib/dev/qat/qat_895xcc.bin and /dev/null differ
diff --git a/sys/contrib/dev/qat/qat_895xcc_mmp.bin b/sys/contrib/dev/qat/qat_895xcc_mmp.bin
deleted file mode 100644
index b0b3e7d8e3d2..000000000000
Binary files a/sys/contrib/dev/qat/qat_895xcc_mmp.bin and /dev/null differ
diff --git a/sys/contrib/dev/qat/qat_c3xxx.bin b/sys/contrib/dev/qat/qat_c3xxx.bin
deleted file mode 100644
index ad8f81c5c331..000000000000
Binary files a/sys/contrib/dev/qat/qat_c3xxx.bin and /dev/null differ
diff --git a/sys/contrib/dev/qat/qat_c3xxx_mmp.bin b/sys/contrib/dev/qat/qat_c3xxx_mmp.bin
deleted file mode 100644
index dfbf3ae5a19e..000000000000
Binary files a/sys/contrib/dev/qat/qat_c3xxx_mmp.bin and /dev/null differ
diff --git a/sys/contrib/dev/qat/qat_c62x.bin b/sys/contrib/dev/qat/qat_c62x.bin
deleted file mode 100644
index fe7fa07b0d05..000000000000
Binary files a/sys/contrib/dev/qat/qat_c62x.bin and /dev/null differ
diff --git a/sys/contrib/dev/qat/qat_c62x_mmp.bin b/sys/contrib/dev/qat/qat_c62x_mmp.bin
deleted file mode 100644
index 829861d4d498..000000000000
Binary files a/sys/contrib/dev/qat/qat_c62x_mmp.bin and /dev/null differ
diff --git a/sys/contrib/dev/qat/qat_d15xx.bin b/sys/contrib/dev/qat/qat_d15xx.bin
deleted file mode 100644
index 26786a704cc5..000000000000
Binary files a/sys/contrib/dev/qat/qat_d15xx.bin and /dev/null differ
diff --git a/sys/contrib/dev/qat/qat_d15xx_mmp.bin b/sys/contrib/dev/qat/qat_d15xx_mmp.bin
deleted file mode 100644
index dd84ed5aff92..000000000000
Binary files a/sys/contrib/dev/qat/qat_d15xx_mmp.bin and /dev/null differ
diff --git a/sys/dev/qat/qat_c3xxx.c b/sys/dev/qat/qat_c3xxx.c
deleted file mode 100644
index 83d39da7d0af..000000000000
--- a/sys/dev/qat/qat_c3xxx.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/* $NetBSD: qat_c3xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Copyright(c) 2014 Intel Corporation.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#if 0
-__KERNEL_RCSID(0, "$NetBSD: qat_c3xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
-#endif
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/systm.h>
-
-#include <machine/bus.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include "qatreg.h"
-#include "qat_hw17reg.h"
-#include "qat_c3xxxreg.h"
-#include "qatvar.h"
-#include "qat_hw17var.h"
-
-static uint32_t
-qat_c3xxx_get_accel_mask(struct qat_softc *sc)
-{
- uint32_t fusectl, strap;
-
- fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
- strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C3XXX, 4);
-
- return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_C3XXX) &
- ACCEL_MASK_C3XXX);
-}
-
-static uint32_t
-qat_c3xxx_get_ae_mask(struct qat_softc *sc)
-{
- uint32_t fusectl, me_strap, me_disable, ssms_disabled;
-
- fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
- me_strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C3XXX, 4);
-
- /* If SSMs are disabled, then disable the corresponding MEs */
- ssms_disabled = (~qat_c3xxx_get_accel_mask(sc)) & ACCEL_MASK_C3XXX;
- me_disable = 0x3;
- while (ssms_disabled) {
- if (ssms_disabled & 1)
- me_strap |= me_disable;
- ssms_disabled >>= 1;
- me_disable <<= 2;
- }
-
- return (~(fusectl | me_strap)) & AE_MASK_C3XXX;
-}
-
-static enum qat_sku
-qat_c3xxx_get_sku(struct qat_softc *sc)
-{
- switch (sc->sc_ae_num) {
- case MAX_AE_C3XXX:
- return QAT_SKU_4;
- }
-
- return QAT_SKU_UNKNOWN;
-}
-
-static uint32_t
-qat_c3xxx_get_accel_cap(struct qat_softc *sc)
-{
- uint32_t cap, legfuse, strap;
-
- legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
- strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C3XXX, 4);
-
- cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
- QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
- QAT_ACCEL_CAP_CIPHER +
- QAT_ACCEL_CAP_AUTHENTICATION +
- QAT_ACCEL_CAP_COMPRESSION +
- QAT_ACCEL_CAP_ZUC +
- QAT_ACCEL_CAP_SHA3;
-
- if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
- cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
- cap &= ~QAT_ACCEL_CAP_CIPHER;
- }
- if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
- cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
- if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
- cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
- if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
- cap &= ~QAT_ACCEL_CAP_COMPRESSION;
- if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
- cap &= ~QAT_ACCEL_CAP_ZUC;
-
- if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_PKE_C3XXX)
- cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
- if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_CY_C3XXX)
- cap &= ~QAT_ACCEL_CAP_COMPRESSION;
-
- return cap;
-}
-
-static const char *
-qat_c3xxx_get_fw_uof_name(struct qat_softc *sc)
-{
-
- return AE_FW_UOF_NAME_C3XXX;
-}
-
-static void
-qat_c3xxx_enable_intr(struct qat_softc *sc)
-{
-
- /* Enable bundle and misc interrupts */
- qat_misc_write_4(sc, SMIAPF0_C3XXX, SMIA0_MASK_C3XXX);
- qat_misc_write_4(sc, SMIAPF1_C3XXX, SMIA1_MASK_C3XXX);
-}
-
-/* Worker thread to service arbiter mappings */
-static uint32_t thrd_to_arb_map[] = {
- 0x12222AAA, 0x11222AAA, 0x12222AAA,
- 0x11222AAA, 0x12222AAA, 0x11222AAA
-};
-
-static void
-qat_c3xxx_get_arb_mapping(struct qat_softc *sc, const uint32_t **arb_map_config)
-{
- int i;
-
- for (i = 1; i < MAX_AE_C3XXX; i++) {
- if ((~sc->sc_ae_mask) & (1 << i))
- thrd_to_arb_map[i] = 0;
- }
- *arb_map_config = thrd_to_arb_map;
-}
-
-static void
-qat_c3xxx_enable_error_interrupts(struct qat_softc *sc)
-{
- qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_C3XXX); /* ME0-ME3 */
- qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_C3XXX); /* ME4-ME5 */
- qat_misc_write_4(sc, ERRMSK5, ERRMSK5_CERR_C3XXX); /* SSM2 */
-
- /* Reset everything except VFtoPF1_16. */
- qat_misc_read_write_and_4(sc, ERRMSK3, VF2PF1_16_C3XXX);
-
- /* RI CPP bus interface error detection and reporting. */
- qat_misc_write_4(sc, RICPPINTCTL_C3XXX, RICPP_EN_C3XXX);
-
- /* TI CPP bus interface error detection and reporting. */
- qat_misc_write_4(sc, TICPPINTCTL_C3XXX, TICPP_EN_C3XXX);
-
- /* Enable CFC Error interrupts and logging. */
- qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_C3XXX, CPP_CFC_UE_C3XXX);
-}
-
-static void
-qat_c3xxx_disable_error_interrupts(struct qat_softc *sc)
-{
- /* ME0-ME3 */
- qat_misc_write_4(sc, ERRMSK0, ERRMSK0_UERR_C3XXX | ERRMSK0_CERR_C3XXX);
- /* ME4-ME5 */
- qat_misc_write_4(sc, ERRMSK1, ERRMSK1_UERR_C3XXX | ERRMSK1_CERR_C3XXX);
- /* CPP Push Pull, RI, TI, SSM0-SSM1, CFC */
- qat_misc_write_4(sc, ERRMSK3, ERRMSK3_UERR_C3XXX);
- /* SSM2 */
- qat_misc_write_4(sc, ERRMSK5, ERRMSK5_UERR_C3XXX);
-}
-
-static void
-qat_c3xxx_enable_error_correction(struct qat_softc *sc)
-{
- u_int i, mask;
-
- /* Enable Accel Engine error detection & correction */
- for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
- if (!(mask & 1))
- continue;
- qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_C3XXX(i),
- ENABLE_AE_ECC_ERR_C3XXX);
- qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_C3XXX(i),
- ENABLE_AE_ECC_PARITY_CORR_C3XXX);
- }
-
- /* Enable shared memory error detection & correction */
- for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
- if (!(mask & 1))
- continue;
-
- qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_C3XXX);
- qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_C3XXX);
- qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_C3XXX);
- }
-
- qat_c3xxx_enable_error_interrupts(sc);
-}
-
-const struct qat_hw qat_hw_c3xxx = {
- .qhw_sram_bar_id = BAR_SRAM_ID_C3XXX,
- .qhw_misc_bar_id = BAR_PMISC_ID_C3XXX,
- .qhw_etr_bar_id = BAR_ETR_ID_C3XXX,
- .qhw_cap_global_offset = CAP_GLOBAL_OFFSET_C3XXX,
- .qhw_ae_offset = AE_OFFSET_C3XXX,
- .qhw_ae_local_offset = AE_LOCAL_OFFSET_C3XXX,
- .qhw_etr_bundle_size = ETR_BUNDLE_SIZE_C3XXX,
- .qhw_num_banks = ETR_MAX_BANKS_C3XXX,
- .qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
- .qhw_num_accel = MAX_ACCEL_C3XXX,
- .qhw_num_engines = MAX_AE_C3XXX,
- .qhw_tx_rx_gap = ETR_TX_RX_GAP_C3XXX,
- .qhw_tx_rings_mask = ETR_TX_RINGS_MASK_C3XXX,
- .qhw_clock_per_sec = CLOCK_PER_SEC_C3XXX,
- .qhw_fw_auth = true,
- .qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
- .qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
- .qhw_ring_asym_tx = 0,
- .qhw_ring_asym_rx = 8,
- .qhw_ring_sym_tx = 2,
- .qhw_ring_sym_rx = 10,
- .qhw_mof_fwname = AE_FW_MOF_NAME_C3XXX,
- .qhw_mmp_fwname = AE_FW_MMP_NAME_C3XXX,
- .qhw_prod_type = AE_FW_PROD_TYPE_C3XXX,
- .qhw_get_accel_mask = qat_c3xxx_get_accel_mask,
- .qhw_get_ae_mask = qat_c3xxx_get_ae_mask,
- .qhw_get_sku = qat_c3xxx_get_sku,
- .qhw_get_accel_cap = qat_c3xxx_get_accel_cap,
- .qhw_get_fw_uof_name = qat_c3xxx_get_fw_uof_name,
- .qhw_enable_intr = qat_c3xxx_enable_intr,
- .qhw_init_admin_comms = qat_adm_mailbox_init,
- .qhw_send_admin_init = qat_adm_mailbox_send_init,
- .qhw_init_arb = qat_arb_init,
- .qhw_get_arb_mapping = qat_c3xxx_get_arb_mapping,
- .qhw_enable_error_correction = qat_c3xxx_enable_error_correction,
- .qhw_disable_error_interrupts = qat_c3xxx_disable_error_interrupts,
- .qhw_set_ssm_wdtimer = qat_set_ssm_wdtimer,
- .qhw_check_slice_hang = qat_check_slice_hang,
- .qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
- .qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
- .qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
-};
diff --git a/sys/dev/qat/qat_c3xxxreg.h b/sys/dev/qat/qat_c3xxxreg.h
deleted file mode 100644
index a5cb957e47fe..000000000000
--- a/sys/dev/qat/qat_c3xxxreg.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/* $NetBSD: qat_c3xxxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Copyright(c) 2014 Intel Corporation.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* $FreeBSD$ */
-
-#ifndef _DEV_PCI_QAT_C3XXXREG_H_
-#define _DEV_PCI_QAT_C3XXXREG_H_
-
-/* Max number of accelerators and engines */
-#define MAX_ACCEL_C3XXX 3
-#define MAX_AE_C3XXX 6
-
-/* PCIe BAR index */
-#define BAR_SRAM_ID_C3XXX NO_PCI_REG
-#define BAR_PMISC_ID_C3XXX 0
-#define BAR_ETR_ID_C3XXX 1
-
-/* BAR PMISC sub-regions */
-#define AE_OFFSET_C3XXX 0x20000
-#define AE_LOCAL_OFFSET_C3XXX 0x20800
-#define CAP_GLOBAL_OFFSET_C3XXX 0x30000
-
-#define SOFTSTRAP_REG_C3XXX 0x2EC
-#define SOFTSTRAP_SS_POWERGATE_CY_C3XXX __BIT(23)
-#define SOFTSTRAP_SS_POWERGATE_PKE_C3XXX __BIT(24)
-
-#define ACCEL_REG_OFFSET_C3XXX 16
-#define ACCEL_MASK_C3XXX 0x7
-#define AE_MASK_C3XXX 0x3F
-
-#define SMIAPF0_C3XXX 0x3A028
-#define SMIAPF1_C3XXX 0x3A030
-#define SMIA0_MASK_C3XXX 0xFFFF
-#define SMIA1_MASK_C3XXX 0x1
-
-/* Error detection and correction */
-#define AE_CTX_ENABLES_C3XXX(i) ((i) * 0x1000 + 0x20818)
-#define AE_MISC_CONTROL_C3XXX(i) ((i) * 0x1000 + 0x20960)
-#define ENABLE_AE_ECC_ERR_C3XXX __BIT(28)
-#define ENABLE_AE_ECC_PARITY_CORR_C3XXX (__BIT(24) | __BIT(12))
-#define ERRSSMSH_EN_C3XXX __BIT(3)
-/* BIT(2) enables the logging of push/pull data errors. */
-#define PPERR_EN_C3XXX (__BIT(2))
-
-/* Mask for VF2PF interrupts */
-#define VF2PF1_16_C3XXX (0xFFFF << 9)
-#define ERRSOU3_VF2PF_C3XXX(errsou3) (((errsou3) & 0x01FFFE00) >> 9)
-#define ERRMSK3_VF2PF_C3XXX(vf_mask) (((vf_mask) & 0xFFFF) << 9)
-
-/* Masks for correctable error interrupts. */
-#define ERRMSK0_CERR_C3XXX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
-#define ERRMSK1_CERR_C3XXX (__BIT(8) | __BIT(0))
-#define ERRMSK5_CERR_C3XXX (0)
-
-/* Masks for uncorrectable error interrupts. */
-#define ERRMSK0_UERR_C3XXX (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
-#define ERRMSK1_UERR_C3XXX (__BIT(9) | __BIT(1))
-#define ERRMSK3_UERR_C3XXX (__BIT(6) | __BIT(5) | __BIT(4) | __BIT(3) | \
- __BIT(2) | __BIT(0))
-#define ERRMSK5_UERR_C3XXX (__BIT(16))
-
-/* RI CPP control */
-#define RICPPINTCTL_C3XXX (0x3A000 + 0x110)
-/*
- * BIT(2) enables error detection and reporting on the RI Parity Error.
- * BIT(1) enables error detection and reporting on the RI CPP Pull interface.
- * BIT(0) enables error detection and reporting on the RI CPP Push interface.
- */
-#define RICPP_EN_C3XXX (__BIT(2) | __BIT(1) | __BIT(0))
-
-/* TI CPP control */
-#define TICPPINTCTL_C3XXX (0x3A400 + 0x138)
-/*
- * BIT(3) enables error detection and reporting on the ETR Parity Error.
- * BIT(2) enables error detection and reporting on the TI Parity Error.
- * BIT(1) enables error detection and reporting on the TI CPP Pull interface.
- * BIT(0) enables error detection and reporting on the TI CPP Push interface.
- */
-#define TICPP_EN_C3XXX \
- (__BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
-
-/* CFC Uncorrectable Errors */
-#define CPP_CFC_ERR_CTRL_C3XXX (0x30000 + 0xC00)
-/*
- * BIT(1) enables interrupt.
- * BIT(0) enables detecting and logging of push/pull data errors.
- */
-#define CPP_CFC_UE_C3XXX (__BIT(1) | __BIT(0))
-
-#define SLICEPWRDOWN_C3XXX(i) ((i) * 0x4000 + 0x2C)
-/* Enabling PKE4-PKE0. */
-#define MMP_PWR_UP_MSK_C3XXX \
- (__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
-
-/* CPM Uncorrectable Errors */
-#define INTMASKSSM_C3XXX(i) ((i) * 0x4000 + 0x0)
-/* Disabling interrupts for correctable errors. */
-#define INTMASKSSM_UERR_C3XXX \
- (__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
-
-/* MMP */
-/* BIT(3) enables correction. */
-#define CERRSSMMMP_EN_C3XXX (__BIT(3))
-
-/* BIT(3) enables logging. */
-#define UERRSSMMMP_EN_C3XXX (__BIT(3))
-
-/* ETR */
-#define ETR_MAX_BANKS_C3XXX 16
-#define ETR_TX_RX_GAP_C3XXX 8
-#define ETR_TX_RINGS_MASK_C3XXX 0xFF
-#define ETR_BUNDLE_SIZE_C3XXX 0x1000
-
-/* AE firmware */
-#define AE_FW_PROD_TYPE_C3XXX 0x02000000
-#define AE_FW_MOF_NAME_C3XXX "qat_c3xxxfw"
-#define AE_FW_MMP_NAME_C3XXX "qat_c3xxx_mmp"
-#define AE_FW_UOF_NAME_C3XXX "icp_qat_ae.suof"
-
-/* Clock frequency */
-#define CLOCK_PER_SEC_C3XXX (685 * 1000000 / 16)
-
-#endif
diff --git a/sys/dev/qat/qat_c62x.c b/sys/dev/qat/qat_c62x.c
deleted file mode 100644
index 826c68db9854..000000000000
--- a/sys/dev/qat/qat_c62x.c
+++ /dev/null
@@ -1,314 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/* $NetBSD: qat_c62x.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Copyright(c) 2014 Intel Corporation.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#if 0
-__KERNEL_RCSID(0, "$NetBSD: qat_c62x.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
-#endif
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/systm.h>
-
-#include <machine/bus.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include "qatreg.h"
-#include "qat_hw17reg.h"
-#include "qat_c62xreg.h"
-#include "qatvar.h"
-#include "qat_hw17var.h"
-
-static uint32_t
-qat_c62x_get_accel_mask(struct qat_softc *sc)
-{
- uint32_t fusectl, strap;
-
- fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
- strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C62X, 4);
-
- return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_C62X) &
- ACCEL_MASK_C62X);
-}
-
-static uint32_t
-qat_c62x_get_ae_mask(struct qat_softc *sc)
-{
- uint32_t fusectl, me_strap, me_disable, ssms_disabled;
-
- fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
- me_strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C62X, 4);
-
- /* If SSMs are disabled, then disable the corresponding MEs */
- ssms_disabled = (~qat_c62x_get_accel_mask(sc)) & ACCEL_MASK_C62X;
- me_disable = 0x3;
- while (ssms_disabled) {
- if (ssms_disabled & 1)
- me_strap |= me_disable;
- ssms_disabled >>= 1;
- me_disable <<= 2;
- }
-
- return (~(fusectl | me_strap)) & AE_MASK_C62X;
-}
-
-static enum qat_sku
-qat_c62x_get_sku(struct qat_softc *sc)
-{
- switch (sc->sc_ae_num) {
- case 8:
- return QAT_SKU_2;
- case MAX_AE_C62X:
- return QAT_SKU_4;
- }
-
- return QAT_SKU_UNKNOWN;
-}
-
-static uint32_t
-qat_c62x_get_accel_cap(struct qat_softc *sc)
-{
- uint32_t cap, legfuse, strap;
-
- legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
- strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C62X, 4);
-
- cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
- QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
- QAT_ACCEL_CAP_CIPHER +
- QAT_ACCEL_CAP_AUTHENTICATION +
- QAT_ACCEL_CAP_COMPRESSION +
- QAT_ACCEL_CAP_ZUC +
- QAT_ACCEL_CAP_SHA3;
-
- if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
- cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
- cap &= ~QAT_ACCEL_CAP_CIPHER;
- }
- if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
- cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
- if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
- cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
- if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
- cap &= ~QAT_ACCEL_CAP_COMPRESSION;
- if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
- cap &= ~QAT_ACCEL_CAP_ZUC;
-
- if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_PKE_C62X)
- cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
- if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_CY_C62X)
- cap &= ~QAT_ACCEL_CAP_COMPRESSION;
-
- return cap;
-}
-
-static const char *
-qat_c62x_get_fw_uof_name(struct qat_softc *sc)
-{
-
- return AE_FW_UOF_NAME_C62X;
-}
-
-static void
-qat_c62x_enable_intr(struct qat_softc *sc)
-{
-
- /* Enable bundle and misc interrupts */
- qat_misc_write_4(sc, SMIAPF0_C62X, SMIA0_MASK_C62X);
- qat_misc_write_4(sc, SMIAPF1_C62X, SMIA1_MASK_C62X);
-}
-
-/* Worker thread to service arbiter mappings */
-static uint32_t thrd_to_arb_map[] = {
- 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
- 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
-};
-
-static void
-qat_c62x_get_arb_mapping(struct qat_softc *sc, const uint32_t **arb_map_config)
-{
- int i;
-
- for (i = 1; i < MAX_AE_C62X; i++) {
- if ((~sc->sc_ae_mask) & (1 << i))
- thrd_to_arb_map[i] = 0;
- }
- *arb_map_config = thrd_to_arb_map;
-}
-
-static void
-qat_c62x_enable_error_interrupts(struct qat_softc *sc)
-{
- qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_C62X); /* ME0-ME3 */
- qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_C62X); /* ME4-ME7 */
- qat_misc_write_4(sc, ERRMSK4, ERRMSK4_CERR_C62X); /* ME8-ME9 */
- qat_misc_write_4(sc, ERRMSK5, ERRMSK5_CERR_C62X); /* SSM2-SSM4 */
-
- /* Reset everything except VFtoPF1_16. */
- qat_misc_read_write_and_4(sc, ERRMSK3, VF2PF1_16_C62X);
- /* Disable Secure RAM correctable error interrupt */
- qat_misc_read_write_or_4(sc, ERRMSK3, ERRMSK3_CERR_C62X);
-
- /* RI CPP bus interface error detection and reporting. */
- qat_misc_write_4(sc, RICPPINTCTL_C62X, RICPP_EN_C62X);
-
- /* TI CPP bus interface error detection and reporting. */
- qat_misc_write_4(sc, TICPPINTCTL_C62X, TICPP_EN_C62X);
-
- /* Enable CFC Error interrupts and logging. */
- qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_C62X, CPP_CFC_UE_C62X);
-
- /* Enable SecureRAM to fix and log Correctable errors */
- qat_misc_write_4(sc, SECRAMCERR_C62X, SECRAM_CERR_C62X);
-
- /* Enable SecureRAM Uncorrectable error interrupts and logging */
- qat_misc_write_4(sc, SECRAMUERR, SECRAM_UERR_C62X);
-
- /* Enable Push/Pull Misc Uncorrectable error interrupts and logging */
- qat_misc_write_4(sc, CPPMEMTGTERR, TGT_UERR_C62X);
-}
-
-static void
-qat_c62x_disable_error_interrupts(struct qat_softc *sc)
-{
- /* ME0-ME3 */
- qat_misc_write_4(sc, ERRMSK0, ERRMSK0_UERR_C62X | ERRMSK0_CERR_C62X);
- /* ME4-ME7 */
- qat_misc_write_4(sc, ERRMSK1, ERRMSK1_UERR_C62X | ERRMSK1_CERR_C62X);
- /* Secure RAM, CPP Push Pull, RI, TI, SSM0-SSM1, CFC */
- qat_misc_write_4(sc, ERRMSK3, ERRMSK3_UERR_C62X | ERRMSK3_CERR_C62X);
- /* ME8-ME9 */
- qat_misc_write_4(sc, ERRMSK4, ERRMSK4_UERR_C62X | ERRMSK4_CERR_C62X);
- /* SSM2-SSM4 */
- qat_misc_write_4(sc, ERRMSK5, ERRMSK5_UERR_C62X | ERRMSK5_CERR_C62X);
-}
-
-static void
-qat_c62x_enable_error_correction(struct qat_softc *sc)
-{
- u_int i, mask;
-
- /* Enable Accel Engine error detection & correction */
- for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
- if (!(mask & 1))
- continue;
- qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_C62X(i),
- ENABLE_AE_ECC_ERR_C62X);
- qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_C62X(i),
- ENABLE_AE_ECC_PARITY_CORR_C62X);
- }
-
- /* Enable shared memory error detection & correction */
- for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
- if (!(mask & 1))
- continue;
-
- qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_C62X);
- qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_C62X);
- qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_C62X);
*** 4652 LINES SKIPPED ***