From nobody Tue Jan 11 00:33:32 2022 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id BD7E01938228 for ; Tue, 11 Jan 2022 00:33:50 +0000 (UTC) (envelope-from wlosh@bsdimp.com) Received: from mail-ua1-x932.google.com (mail-ua1-x932.google.com [IPv6:2607:f8b0:4864:20::932]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4JXsBQ4ZjNz3hHr for ; Tue, 11 Jan 2022 00:33:50 +0000 (UTC) (envelope-from wlosh@bsdimp.com) Received: by mail-ua1-x932.google.com with SMTP id c36so26697378uae.13 for ; Mon, 10 Jan 2022 16:33:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=iSsU6wWSzU7D2MYkMTmuY4atTykRIxTNyxlCQ55oxkU=; b=m0YRKzP0XdbDSUUjLgDKEJJ/WZp1kCRGWtUV7DYoFMRWyRP6lQdU0HHGV5mlQanc3Q WoCKH4BmqhDvqnGgfS7yB1/iwwInykdV9J398BKBsm2/Cs1GyEL5/tx4ONZRKUwOZMI7 84CgXlKACzUYJl89FZEx3zriLLNW32NsH/ubB40UO0nCBcrzzVDXmx+HI+gkXSBq+wg3 1kqmMHhBeG6/E5diIOd1VvgyhnZEyJEd2VPrTTJs2jnsbFTo3iVRUxc6ICL6ew2KvZhU su0H28lxeYRxuVJm8Rz5ggi3763E2TIw8k2yS8mbsCNAJquzyeRtp96iTJxuU0lP+kEp sl9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=iSsU6wWSzU7D2MYkMTmuY4atTykRIxTNyxlCQ55oxkU=; b=Bshb0UtqwAAFfk5eGCHZUX7hbcmtq2yEedpyu06TTkdgtZlYSFabuJazUYORwTwOXt p0RPsGkkHEgPP38qsAspiy5HsHmTPJ1+3lPqNahrl+xsuZsG09Iuy09Dz0+qfrwzJQ9J AhaL+5Z8SZoaXOnbKSSH28JYdNq0RWvqMAiPDcPy4yzR2yvKDpwI9GH4Tdxgb2p14XtK th3rCJd+3FwsudPFP/Cic4aDLuWBkbcdx+pwGFZL58Z1aEkzSuNUsEC9iYXc3/NsLnET dMMU4ueuzdsTBCZQCs2WeoZjVSJgL8icVfoR2Rp1Bw+AJJLlz7sI598aoHzh3sex7GrF AgsA== X-Gm-Message-State: AOAM5335+fZ2ZsJQCU00n114/ztOerhq2/soRMFhMvC7p854UgUYcyVi /R+sEFM/gRAqFoC9Haz3qZB7dK7EgXm1FO98cDtVAg== X-Google-Smtp-Source: ABdhPJyXT4K46Xv/tYhL7aOVfeXXVroxnDbRdBGh1DEve/aRfWPtukuGk0hMcIxZ80RQrG8+wIoa9xfHfmgdyrOEoPI= X-Received: by 2002:a05:6102:ec2:: with SMTP id m2mr1153783vst.6.1641861223605; Mon, 10 Jan 2022 16:33:43 -0800 (PST) List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-main@freebsd.org X-BeenThere: dev-commits-src-main@freebsd.org MIME-Version: 1.0 References: <202201071627.207GRsGX062055@gitrepo.freebsd.org> <45275428-75e2-aaae-bed3-e5e84b39e17c@FreeBSD.org> <61fa2498-3516-0f1b-fb24-270d38f0472f@FreeBSD.org> In-Reply-To: From: Warner Losh Date: Mon, 10 Jan 2022 17:33:32 -0700 Message-ID: Subject: Re: git: d6c0538dae8d - main - ddb: Remove SOFTWARE_SSTEP support To: Olivier Houchard Cc: John Baldwin , Warner Losh , src-committers , "" , dev-commits-src-main@freebsd.org Content-Type: multipart/alternative; boundary="00000000000000fe8305d5439b7c" X-Rspamd-Queue-Id: 4JXsBQ4ZjNz3hHr X-Spamd-Bar: ---- Authentication-Results: mx1.freebsd.org; none X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[] X-ThisMailContainsUnwantedMimeParts: N --00000000000000fe8305d5439b7c Content-Type: text/plain; charset="UTF-8" On Mon, Jan 10, 2022 at 4:27 PM Olivier Houchard wrote: > On Mon, Jan 10, 2022 at 02:50:40PM -0800, John Baldwin wrote: > > On 1/10/22 1:37 PM, Olivier Houchard wrote: > > > On Mon, Jan 10, 2022 at 02:14:54PM -0700, Warner Losh wrote: > > >> On Mon, Jan 10, 2022 at 12:48 PM John Baldwin > wrote: > > >> > > >>> On 1/7/22 8:27 AM, Warner Losh wrote: > > >>>> The branch main has been updated by imp: > > >>>> > > >>>> URL: > > >>> > https://cgit.FreeBSD.org/src/commit/?id=d6c0538dae8d138219dfd051994a44c50e741212 > > >>>> > > >>>> commit d6c0538dae8d138219dfd051994a44c50e741212 > > >>>> Author: Warner Losh > > >>>> AuthorDate: 2022-01-07 16:25:33 +0000 > > >>>> Commit: Warner Losh > > >>>> CommitDate: 2022-01-07 16:25:33 +0000 > > >>>> > > >>>> ddb: Remove SOFTWARE_SSTEP support > > >>>> > > >>>> It was needed for mips only, and only kinda sorta worked for > mips. > > >>> It > > >>>> can be brought back if we grow another architecture that need > it. > > >>>> > > >>>> Sponsored by: Netflix > > >>> > > >>> RISC-V would need it in theory (no hardware single step), but no one > has > > >>> felt the > > >>> need to implement the backend support for it. I think 32-bit arm > doesn't > > >>> support > > >>> hardware single step either (but again, no one has bothered to add > the > > >>> backend > > >>> support). > > >>> > > >> > > >> Generally, I agree with these thoughts. I went ahead with the removal > > >> because I > > >> knew it would be easy to bring back, even years from now should > someone[tm] > > >> have an implementation for those platforms (though I thought 32-bit > arm did > > >> have > > >> single step in hardware). > > >> > > >> Should I put it back? Or should we wait until someone shows up with > support > > >> for > > >> a supported platform? > > >> > > > > > > It was used for arm, but only older arm, ie v4/v5, pretty sure newer > > > cores do have hardware breakpoints. > > > > They have hardware breakpoints/watchpoints, not sure if they have single > step. > > > > In GDB 32-bit arm only supports software single step, even on Linux. > > > > Seems true, the newer code just seems to use hardware breakpoints, but > the logic is the same as what was done with SOFTWARE_SSTEP. > If there's a backend for armv7 that shows up, we can put this back :) I was confused between hardware breakpoints and single step. Warner --00000000000000fe8305d5439b7c Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Mon, Jan 10, 2022 at 4:27 PM Olivi= er Houchard <cognet@ci0.org> wr= ote:
On Mon, Jan= 10, 2022 at 02:50:40PM -0800, John Baldwin wrote:
> On 1/10/22 1:37 PM, Olivier Houchard wrote:
> > On Mon, Jan 10, 2022 at 02:14:54PM -0700, Warner Losh wrote:
> >> On Mon, Jan 10, 2022 at 12:48 PM John Baldwin <jhb@freebsd.org> wrote: > >>
> >>> On 1/7/22 8:27 AM, Warner Losh wrote:
> >>>> The branch main has been updated by imp:
> >>>>
> >>>> URL:
> >>> = https://cgit.FreeBSD.org/src/commit/?id=3Dd6c0538dae8d138219dfd051994a44c50= e741212
> >>>>
> >>>> commit d6c0538dae8d138219dfd051994a44c50e741212
> >>>> Author:=C2=A0 =C2=A0 =C2=A0Warner Losh <imp@FreeBS= D.org>
> >>>> AuthorDate: 2022-01-07 16:25:33 +0000
> >>>> Commit:=C2=A0 =C2=A0 =C2=A0Warner Losh <imp@FreeBS= D.org>
> >>>> CommitDate: 2022-01-07 16:25:33 +0000
> >>>>
> >>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0ddb: Remove SOFTWARE_SSTEP = support
> >>>>
> >>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0It was needed for mips only= , and only kinda sorta worked for mips.
> >>> It
> >>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0can be brought back if we g= row another architecture that need it.
> >>>>
> >>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0Sponsored by:=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0Netflix
> >>>
> >>> RISC-V would need it in theory (no hardware single step),= but no one has
> >>> felt the
> >>> need to implement the backend support for it.=C2=A0 I thi= nk 32-bit arm doesn't
> >>> support
> >>> hardware single step either (but again, no one has bother= ed to add the
> >>> backend
> >>> support).
> >>>
> >>
> >> Generally, I agree with these thoughts. I went ahead with the= removal
> >> because I
> >> knew it would be easy to bring back, even years from now shou= ld someone[tm]
> >> have an implementation for those platforms (though I thought = 32-bit arm did
> >> have
> >> single step in hardware).
> >>
> >> Should I put it back? Or should we wait until someone shows u= p with support
> >> for
> >> a supported platform?
> >>
> >
> > It was used for arm, but only older arm, ie v4/v5, pretty sure ne= wer
> > cores do have hardware breakpoints.
>
> They have hardware breakpoints/watchpoints, not sure if they have sing= le step.
>
> In GDB 32-bit arm only supports software single step, even on Linux. >

Seems true, the newer code just seems to use hardware breakpoints, but
the logic is the same as what was done with SOFTWARE_SSTEP.

If there's a backend for armv7 that shows up, we c= an put this back :)

I was confused between hardwar= e breakpoints and single step.

Warner
<= /div> --00000000000000fe8305d5439b7c--