git: 8f216d282c3d - main - Restore original MDC speed control register value after MAC reset, if it wasn't default

The branch main has been updated by kevlo:

URL: https://cgit.FreeBSD.org/src/commit/?id=8f216d282c3d874bd0f73f55a2801b9d15451213

commit 8f216d282c3d874bd0f73f55a2801b9d15451213
Author:     Kevin Lo <kevlo@FreeBSD.org>
AuthorDate: 2022-04-25 01:56:20 +0000
Commit:     Kevin Lo <kevlo@FreeBSD.org>
CommitDate: 2022-04-25 01:56:20 +0000

    Restore original MDC speed control register value after MAC reset, if it
    wasn't default
    
    Since vte_reset changes register value to MDCSC_DEFAULT value, which may not
    be the original value, thus causing some phy registers read failures.
    Restoring VTE_MDCSC value to original after reset solves the link state
    flapping issue.
    
    Thanks to jhb ("the code looks ok") for his review.
    Reviewed by:    jhb
    Obtained from:  NetBSD via Andrius V
    Differential Revision:  https://reviews.freebsd.org/D34956
---
 sys/dev/vte/if_vte.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/sys/dev/vte/if_vte.c b/sys/dev/vte/if_vte.c
index b6bf909037e1..98e5a14e1399 100644
--- a/sys/dev/vte/if_vte.c
+++ b/sys/dev/vte/if_vte.c
@@ -1605,9 +1605,10 @@ vte_tick(void *arg)
 static void
 vte_reset(struct vte_softc *sc)
 {
-	uint16_t mcr;
+	uint16_t mcr, mdcsc;
 	int i;
 
+	mdcsc = CSR_READ_2(sc, VTE_MDCSC);
 	mcr = CSR_READ_2(sc, VTE_MCR1);
 	CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
 	for (i = VTE_RESET_TIMEOUT; i > 0; i--) {
@@ -1625,6 +1626,14 @@ vte_reset(struct vte_softc *sc)
 	CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
 	CSR_WRITE_2(sc, VTE_MACSM, 0);
 	DELAY(5000);
+
+	/*
+	 * On some SoCs (like Vortex86DX3) MDC speed control register value
+	 * needs to be restored to original value instead of default one,
+	 * otherwise some PHY registers may fail to be read.
+	 */
+	if (mdcsc != MDCSC_DEFAULT)
+		CSR_WRITE_2(sc, VTE_MDCSC, mdcsc);
 }
 
 static void