git: 355c15130aef - main - iwm: update if_iwmreg.h to the latest (as of today) openbsd changes
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Date: Wed, 27 Oct 2021 03:29:44 UTC
The branch main has been updated by adrian:
URL: https://cgit.FreeBSD.org/src/commit/?id=355c15130aef13484821051a655da9b9066e1015
commit 355c15130aef13484821051a655da9b9066e1015
Author: Adrian Chadd <adrian@FreeBSD.org>
AuthorDate: 2021-10-24 15:47:04 +0000
Commit: Adrian Chadd <adrian@FreeBSD.org>
CommitDate: 2021-10-27 03:28:54 +0000
iwm: update if_iwmreg.h to the latest (as of today) openbsd changes
Summary:
This updates the if_iwmreg.h definitions to;
OpenBSD: if_iwmreg.h,v 1.65 2021/10/11 09:03:22 stsp Exp
A few things haven't been fully converted, namely:
* I left a couple things as enums for now just to reduce the
other diffs needed; but they're the same values
* The IWM_SCD_QUEUE_* macros have different offsets which I
didn't update in case they broke things / changed based on later
firmware. But they also may be real bugfixes which are needed
for later chips. It'll need more testing before flipping this on.
The c file updates are:
* Use the newer names for things if the name changed but the semantics
didn't
* Explicitly use the earlier firmware structs which maintain compat
with the current firmware and code. The newer ones are in here and
they'll get converted when more openbsd code is merged into this tree.
* Use the older iwm rate table for now, which has entries for legacy
rates, HT and VHT. Our code works with that right now, updating it
to openbsd's err, "different" version can be done at a later date
when HT/VHT support is added.
Notably, a bunch of definitions were deleted that weren't used.
They're not used either in the openbsd/dfbsd drivers so I think it's
safe to delete them in the long run.
Test Plan: 7260 hw 0x140
Subscribers: imp
Differential Revision: https://reviews.freebsd.org/D32627
Reviewed by: md5
Obtained From: OpenBSD
---
sys/dev/iwm/if_iwm.c | 112 +-
sys/dev/iwm/if_iwm_binding.c | 2 +-
sys/dev/iwm/if_iwm_phy_db.c | 37 +-
sys/dev/iwm/if_iwm_scan.c | 10 +-
sys/dev/iwm/if_iwmreg.h | 3522 ++++++++++++++++++++++++------------------
sys/dev/iwm/if_iwmvar.h | 2 +-
6 files changed, 2030 insertions(+), 1655 deletions(-)
diff --git a/sys/dev/iwm/if_iwm.c b/sys/dev/iwm/if_iwm.c
index f994e8e75307..3e34c3cac98e 100644
--- a/sys/dev/iwm/if_iwm.c
+++ b/sys/dev/iwm/if_iwm.c
@@ -1914,98 +1914,6 @@ iwm_nvm_read_section(struct iwm_softc *sc,
/* iwlwifi/iwl-nvm-parse.c */
-/* NVM offsets (in words) definitions */
-enum iwm_nvm_offsets {
- /* NVM HW-Section offset (in words) definitions */
- IWM_HW_ADDR = 0x15,
-
-/* NVM SW-Section offset (in words) definitions */
- IWM_NVM_SW_SECTION = 0x1C0,
- IWM_NVM_VERSION = 0,
- IWM_RADIO_CFG = 1,
- IWM_SKU = 2,
- IWM_N_HW_ADDRS = 3,
- IWM_NVM_CHANNELS = 0x1E0 - IWM_NVM_SW_SECTION,
-
-/* NVM calibration section offset (in words) definitions */
- IWM_NVM_CALIB_SECTION = 0x2B8,
- IWM_XTAL_CALIB = 0x316 - IWM_NVM_CALIB_SECTION
-};
-
-enum iwm_8000_nvm_offsets {
- /* NVM HW-Section offset (in words) definitions */
- IWM_HW_ADDR0_WFPM_8000 = 0x12,
- IWM_HW_ADDR1_WFPM_8000 = 0x16,
- IWM_HW_ADDR0_PCIE_8000 = 0x8A,
- IWM_HW_ADDR1_PCIE_8000 = 0x8E,
- IWM_MAC_ADDRESS_OVERRIDE_8000 = 1,
-
- /* NVM SW-Section offset (in words) definitions */
- IWM_NVM_SW_SECTION_8000 = 0x1C0,
- IWM_NVM_VERSION_8000 = 0,
- IWM_RADIO_CFG_8000 = 0,
- IWM_SKU_8000 = 2,
- IWM_N_HW_ADDRS_8000 = 3,
-
- /* NVM REGULATORY -Section offset (in words) definitions */
- IWM_NVM_CHANNELS_8000 = 0,
- IWM_NVM_LAR_OFFSET_8000_OLD = 0x4C7,
- IWM_NVM_LAR_OFFSET_8000 = 0x507,
- IWM_NVM_LAR_ENABLED_8000 = 0x7,
-
- /* NVM calibration section offset (in words) definitions */
- IWM_NVM_CALIB_SECTION_8000 = 0x2B8,
- IWM_XTAL_CALIB_8000 = 0x316 - IWM_NVM_CALIB_SECTION_8000
-};
-
-/* SKU Capabilities (actual values from NVM definition) */
-enum nvm_sku_bits {
- IWM_NVM_SKU_CAP_BAND_24GHZ = (1 << 0),
- IWM_NVM_SKU_CAP_BAND_52GHZ = (1 << 1),
- IWM_NVM_SKU_CAP_11N_ENABLE = (1 << 2),
- IWM_NVM_SKU_CAP_11AC_ENABLE = (1 << 3),
-};
-
-/* radio config bits (actual values from NVM definition) */
-#define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */
-#define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
-#define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
-#define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
-#define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
-#define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
-
-#define IWM_NVM_RF_CFG_FLAVOR_MSK_8000(x) (x & 0xF)
-#define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF)
-#define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF)
-#define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF)
-#define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF)
-#define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF)
-
-/**
- * enum iwm_nvm_channel_flags - channel flags in NVM
- * @IWM_NVM_CHANNEL_VALID: channel is usable for this SKU/geo
- * @IWM_NVM_CHANNEL_IBSS: usable as an IBSS channel
- * @IWM_NVM_CHANNEL_ACTIVE: active scanning allowed
- * @IWM_NVM_CHANNEL_RADAR: radar detection required
- * XXX cannot find this (DFS) flag in iwm-nvm-parse.c
- * @IWM_NVM_CHANNEL_DFS: dynamic freq selection candidate
- * @IWM_NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
- * @IWM_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
- * @IWM_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
- * @IWM_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
- */
-enum iwm_nvm_channel_flags {
- IWM_NVM_CHANNEL_VALID = (1 << 0),
- IWM_NVM_CHANNEL_IBSS = (1 << 1),
- IWM_NVM_CHANNEL_ACTIVE = (1 << 3),
- IWM_NVM_CHANNEL_RADAR = (1 << 4),
- IWM_NVM_CHANNEL_DFS = (1 << 7),
- IWM_NVM_CHANNEL_WIDE = (1 << 8),
- IWM_NVM_CHANNEL_40MHZ = (1 << 9),
- IWM_NVM_CHANNEL_80MHZ = (1 << 10),
- IWM_NVM_CHANNEL_160MHZ = (1 << 11),
-};
-
/*
* Translate EEPROM flags to net80211.
*/
@@ -2220,7 +2128,7 @@ iwm_set_radio_cfg(const struct iwm_softc *sc, struct iwm_nvm_data *data,
data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK_8000(radio_cfg);
data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK_8000(radio_cfg);
data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK_8000(radio_cfg);
- data->radio_cfg_pnum = IWM_NVM_RF_CFG_FLAVOR_MSK_8000(radio_cfg);
+ data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK_8000(radio_cfg);
data->valid_tx_ant = IWM_NVM_RF_CFG_TX_ANT_MSK_8000(radio_cfg);
data->valid_rx_ant = IWM_NVM_RF_CFG_RX_ANT_MSK_8000(radio_cfg);
}
@@ -2383,7 +2291,7 @@ iwm_parse_nvm_sections(struct iwm_softc *sc, struct iwm_nvm_section *sections)
static int
iwm_nvm_init(struct iwm_softc *sc)
{
- struct iwm_nvm_section nvm_sections[IWM_NVM_MAX_NUM_SECTIONS];
+ struct iwm_nvm_section nvm_sections[IWM_NVM_NUM_OF_SECTIONS];
int i, ret, section;
uint32_t size_read = 0;
uint8_t *nvm_buffer, *temp;
@@ -2391,7 +2299,7 @@ iwm_nvm_init(struct iwm_softc *sc)
memset(nvm_sections, 0, sizeof(nvm_sections));
- if (sc->cfg->nvm_hw_section_num >= IWM_NVM_MAX_NUM_SECTIONS)
+ if (sc->cfg->nvm_hw_section_num >= IWM_NVM_NUM_OF_SECTIONS)
return EINVAL;
/* load NVM values from nic */
@@ -2401,7 +2309,7 @@ iwm_nvm_init(struct iwm_softc *sc)
nvm_buffer = malloc(sc->cfg->eeprom_size, M_DEVBUF, M_NOWAIT | M_ZERO);
if (!nvm_buffer)
return ENOMEM;
- for (section = 0; section < IWM_NVM_MAX_NUM_SECTIONS; section++) {
+ for (section = 0; section < IWM_NVM_NUM_OF_SECTIONS; section++) {
/* we override the constness for initial read */
ret = iwm_nvm_read_section(sc, section, nvm_buffer,
&len, size_read);
@@ -2428,7 +2336,7 @@ iwm_nvm_init(struct iwm_softc *sc)
IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET,
"nvm version = %x\n", sc->nvm_data->nvm_version);
- for (i = 0; i < IWM_NVM_MAX_NUM_SECTIONS; i++) {
+ for (i = 0; i < IWM_NVM_NUM_OF_SECTIONS; i++) {
if (nvm_sections[i].data != NULL)
free(nvm_sections[i].data, M_DEVBUF);
}
@@ -3181,7 +3089,7 @@ iwm_get_noise(struct iwm_softc *sc,
static void
iwm_handle_rx_statistics(struct iwm_softc *sc, struct iwm_rx_packet *pkt)
{
- struct iwm_notif_statistics_v10 *stats = (void *)&pkt->data;
+ struct iwm_notif_statistics *stats = (void *)&pkt->data;
memcpy(&sc->sc_stats, stats, sizeof(sc->sc_stats));
sc->sc_noise = iwm_get_noise(sc, &stats->rx.general);
@@ -3897,7 +3805,7 @@ iwm_tx(struct iwm_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac)
if (hdrlen & 3) {
/* First segment length must be a multiple of 4. */
flags |= IWM_TX_CMD_FLG_MH_PAD;
- tx->offload_assist |= htole16(1 << IWM_TX_CMD_OFFLD_PAD);
+ tx->offload_assist |= htole16(IWM_TX_CMD_OFFLD_PAD);
pad = 4 - (hdrlen & 3);
} else {
tx->offload_assist = 0;
@@ -4059,7 +3967,7 @@ int
iwm_flush_tx_path(struct iwm_softc *sc, uint32_t tfd_msk, uint32_t flags)
{
int ret;
- struct iwm_tx_path_flush_cmd flush_cmd = {
+ struct iwm_tx_path_flush_cmd_v1 flush_cmd = {
.queues_ctl = htole32(tfd_msk),
.flush_ctl = htole16(IWM_DUMP_TX_FIFO_FLUSH),
};
@@ -4079,7 +3987,7 @@ iwm_flush_tx_path(struct iwm_softc *sc, uint32_t tfd_msk, uint32_t flags)
static int
iwm_update_quotas(struct iwm_softc *sc, struct iwm_vap *ivp)
{
- struct iwm_time_quota_cmd cmd;
+ struct iwm_time_quota_cmd_v1 cmd;
int i, idx, ret, num_active_macs, quota, quota_rem;
int colors[IWM_MAX_BINDINGS] = { -1, -1, -1, -1, };
int n_ifs[IWM_MAX_BINDINGS] = {0, };
@@ -4711,7 +4619,7 @@ iwm_send_update_mcc_cmd(struct iwm_softc *sc, const char *alpha2)
#ifdef IWM_DEBUG
struct iwm_rx_packet *pkt;
struct iwm_mcc_update_resp_v1 *mcc_resp_v1 = NULL;
- struct iwm_mcc_update_resp *mcc_resp;
+ struct iwm_mcc_update_resp_v2 *mcc_resp;
int n_channels;
uint16_t mcc;
#endif
diff --git a/sys/dev/iwm/if_iwm_binding.c b/sys/dev/iwm/if_iwm_binding.c
index 28207c998d77..6b0b19b7515c 100644
--- a/sys/dev/iwm/if_iwm_binding.c
+++ b/sys/dev/iwm/if_iwm_binding.c
@@ -159,7 +159,7 @@ static int
iwm_binding_cmd(struct iwm_softc *sc, uint32_t action,
struct iwm_iface_iterator_data *data)
{
- struct iwm_binding_cmd cmd;
+ struct iwm_binding_cmd_v1 cmd;
struct iwm_phy_ctxt *phyctxt = data->phyctxt;
int i, ret;
uint32_t status;
diff --git a/sys/dev/iwm/if_iwm_phy_db.c b/sys/dev/iwm/if_iwm_phy_db.c
index 40a0a05adb15..08ded1121d03 100644
--- a/sys/dev/iwm/if_iwm_phy_db.c
+++ b/sys/dev/iwm/if_iwm_phy_db.c
@@ -186,41 +186,6 @@ struct iwm_phy_db {
struct iwm_softc *sc;
};
-enum iwm_phy_db_section_type {
- IWM_PHY_DB_CFG = 1,
- IWM_PHY_DB_CALIB_NCH,
- IWM_PHY_DB_UNUSED,
- IWM_PHY_DB_CALIB_CHG_PAPD,
- IWM_PHY_DB_CALIB_CHG_TXP,
- IWM_PHY_DB_MAX
-};
-
-#define PHY_DB_CMD 0x6c
-
-/*
- * phy db - configure operational ucode
- */
-struct iwm_phy_db_cmd {
- uint16_t type;
- uint16_t length;
- uint8_t data[];
-} __packed;
-
-/* for parsing of tx power channel group data that comes from the firmware*/
-struct iwm_phy_db_chg_txp {
- uint32_t space;
- uint16_t max_channel_idx;
-} __packed;
-
-/*
- * phy db - Receive phy db chunk after calibrations
- */
-struct iwm_calib_res_notif_phy_db {
- uint16_t type;
- uint16_t length;
- uint8_t data[];
-} __packed;
-
struct iwm_phy_db *
iwm_phy_db_init(struct iwm_softc *sc)
{
@@ -477,7 +442,7 @@ iwm_send_phy_db_cmd(struct iwm_phy_db *phy_db, uint16_t type,
{
struct iwm_phy_db_cmd phy_db_cmd;
struct iwm_host_cmd cmd = {
- .id = PHY_DB_CMD,
+ .id = IWM_PHY_DB_CMD,
};
IWM_DPRINTF(phy_db->sc, IWM_DEBUG_RESET,
diff --git a/sys/dev/iwm/if_iwm_scan.c b/sys/dev/iwm/if_iwm_scan.c
index cdf7985d9a97..efba76ad502a 100644
--- a/sys/dev/iwm/if_iwm_scan.c
+++ b/sys/dev/iwm/if_iwm_scan.c
@@ -379,7 +379,7 @@ iwm_umac_scan_fill_channels(struct iwm_softc *sc,
}
static int
-iwm_fill_probe_req(struct iwm_softc *sc, struct iwm_scan_probe_req *preq)
+iwm_fill_probe_req(struct iwm_softc *sc, struct iwm_scan_probe_req_v1 *preq)
{
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
@@ -594,12 +594,12 @@ iwm_scan_size(struct iwm_softc *sc)
return base_size +
sizeof(struct iwm_scan_channel_cfg_umac) *
sc->sc_fw.ucode_capa.n_scan_channels +
- sizeof(struct iwm_scan_req_umac_tail);
+ sizeof(struct iwm_scan_req_umac_tail_v1);
} else {
return sizeof(struct iwm_scan_req_lmac) +
sizeof(struct iwm_scan_channel_cfg_lmac) *
sc->sc_fw.ucode_capa.n_scan_channels +
- sizeof(struct iwm_scan_probe_req);
+ sizeof(struct iwm_scan_probe_req_v1);
}
}
@@ -614,7 +614,7 @@ iwm_umac_scan(struct iwm_softc *sc)
};
struct ieee80211_scan_state *ss = sc->sc_ic.ic_scan;
struct iwm_scan_req_umac *req;
- struct iwm_scan_req_umac_tail *tail;
+ struct iwm_scan_req_umac_tail_v1 *tail;
size_t req_len;
uint16_t general_flags;
uint8_t channel_flags, i, nssid;
@@ -799,7 +799,7 @@ iwm_lmac_scan(struct iwm_softc *sc)
(struct iwm_scan_channel_cfg_lmac *)req->data, nssid);
ret = iwm_fill_probe_req(sc,
- (struct iwm_scan_probe_req *)(req->data +
+ (struct iwm_scan_probe_req_v1 *)(req->data +
(sizeof(struct iwm_scan_channel_cfg_lmac) *
sc->sc_fw.ucode_capa.n_scan_channels)));
if (ret) {
diff --git a/sys/dev/iwm/if_iwmreg.h b/sys/dev/iwm/if_iwmreg.h
index 310b2d53a82e..c3c51a25c4b0 100644
--- a/sys/dev/iwm/if_iwmreg.h
+++ b/sys/dev/iwm/if_iwmreg.h
@@ -1,5 +1,4 @@
-/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
-/* $FreeBSD$ */
+/* $OpenBSD: if_iwmreg.h,v 1.65 2021/10/11 09:03:22 stsp Exp $ */
/******************************************************************************
*
@@ -63,6 +62,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
+
#ifndef __IF_IWM_REG_H__
#define __IF_IWM_REG_H__
@@ -193,7 +193,7 @@
/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
* acknowledged (reset) by host writing "1" to flagged bits. */
-#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
+#define IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
@@ -216,7 +216,7 @@
IWM_CSR_INT_BIT_RX_PERIODIC)
/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
-#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
+#define IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */
#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
@@ -306,7 +306,6 @@ enum {
IWM_SILICON_C_STEP,
};
-
#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
@@ -417,30 +416,131 @@ enum {
#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
/* DRAM INT TABLE */
-#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
+#define IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31)
#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
/* SECURE boot registers */
#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
-enum iwm_secure_boot_config_reg {
- IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
- IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
-};
-
+#define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP 0x00000001
+#define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ 0x00000002
#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
-enum iwm_secure_boot_status_reg {
- IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
- IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
- IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
- IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
- IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
-};
+#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS 0x00000003
+#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED 0x00000002
+#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS 0x00000004
+#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL 0x00000008
+#define IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL 0x00000010
#define IWM_FH_UCODE_LOAD_STATUS 0x1af0
+
#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
+/* 9000 rx series registers */
+
+#define IWM_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */
+#define IWM_RFH_Q_FRBDCB_BA_LSB(q) (IWM_RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
+/* Write index table */
+#define IWM_RFH_Q0_FRBDCB_WIDX 0xA08080
+#define IWM_RFH_Q_FRBDCB_WIDX(q) (IWM_RFH_Q0_FRBDCB_WIDX + (q) * 4)
+/* Write index table - shadow registers */
+#define IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80
+#define IWM_RFH_Q_FRBDCB_WIDX_TRG(q) (IWM_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
+/* Read index table */
+#define IWM_RFH_Q0_FRBDCB_RIDX 0xA080C0
+#define IWM_RFH_Q_FRBDCB_RIDX(q) (IWM_RFH_Q0_FRBDCB_RIDX + (q) * 4)
+/* Used list table */
+#define IWM_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */
+#define IWM_RFH_Q_URBDCB_BA_LSB(q) (IWM_RFH_Q0_URBDCB_BA_LSB + (q) * 8)
+/* Write index table */
+#define IWM_RFH_Q0_URBDCB_WIDX 0xA08180
+#define IWM_RFH_Q_URBDCB_WIDX(q) (IWM_RFH_Q0_URBDCB_WIDX + (q) * 4)
+#define IWM_RFH_Q0_URBDCB_VAID 0xA081C0
+#define IWM_RFH_Q_URBDCB_VAID(q) (IWM_RFH_Q0_URBDCB_VAID + (q) * 4)
+/* stts */
+#define IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */
+#define IWM_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWM_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
+
+#define IWM_RFH_Q0_ORB_WPTR_LSB 0xA08280
+#define IWM_RFH_Q_ORB_WPTR_LSB(q) (IWM_RFH_Q0_ORB_WPTR_LSB + (q) * 8)
+#define IWM_RFH_RBDBUF_RBD0_LSB 0xA08300
+#define IWM_RFH_RBDBUF_RBD_LSB(q) (IWM_RFH_RBDBUF_RBD0_LSB + (q) * 8)
+
+/**
+ * RFH Status Register
+ *
+ * Bit fields:
+ *
+ * Bit 29: RBD_FETCH_IDLE
+ * This status flag is set by the RFH when there is no active RBD fetch from
+ * DRAM.
+ * Once the RFH RBD controller starts fetching (or when there is a pending
+ * RBD read response from DRAM), this flag is immediately turned off.
+ *
+ * Bit 30: SRAM_DMA_IDLE
+ * This status flag is set by the RFH when there is no active transaction from
+ * SRAM to DRAM.
+ * Once the SRAM to DRAM DMA is active, this flag is immediately turned off.
+ *
+ * Bit 31: RXF_DMA_IDLE
+ * This status flag is set by the RFH when there is no active transaction from
+ * RXF to DRAM.
+ * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
+ */
+#define IWM_RFH_GEN_STATUS 0xA09808
+#define IWM_RFH_GEN_STATUS_GEN3 0xA07824
+#define IWM_RBD_FETCH_IDLE (1 << 29)
+#define IWM_SRAM_DMA_IDLE (1 << 30)
+#define IWM_RXF_DMA_IDLE (1U << 31)
+
+/* DMA configuration */
+#define IWM_RFH_RXF_DMA_CFG 0xA09820
+#define IWM_RFH_RXF_DMA_CFG_GEN3 0xA07880
+/* RB size */
+#define IWM_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
+#define IWM_RFH_RXF_DMA_RB_SIZE_POS 16
+#define IWM_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWM_RFH_RXF_DMA_RB_SIZE_POS)
+/* RB Circular Buffer size:defines the table sizes in RBD units */
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_POS 20
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
+#define IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS 24
+#define IWM_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS)
+#define IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
+#define IWM_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
+#define IWM_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
+#define IWM_RFH_DMA_EN_ENABLE_VAL (1U << 31)
+
+#define IWM_RFH_RXF_RXQ_ACTIVE 0xA0980C
+
+#define IWM_RFH_GEN_CFG 0xA09800
+#define IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0)
+#define IWM_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1)
+#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010
+#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000
+/* the driver assumes everywhere that the default RXQ is 0 */
+#define IWM_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00
+
+/* end of 9000 rx series registers */
+
#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
@@ -457,10 +557,6 @@ enum iwm_secure_boot_status_reg {
#define IWM_LMPM_CHICK 0xa01ff8
#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
-#define IWM_UREG_CHICK 0xa05c00
-#define IWM_UREG_CHICK_MSI_ENABLE 0x01000000
-#define IWM_UREG_CHICK_MSIX_ENABLE 0x02000000
-
#define IWM_FH_TCSR_0_REG0 (0x1D00)
/*
@@ -530,6 +626,8 @@ enum iwm_secure_boot_status_reg {
#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
#define IWM_RSA_ENABLE 0xa24b08
#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
+#define IWM_PREG_PRPH_WPROT_9000 0xa04ce0
+#define IWM_PREG_PRPH_WPROT_22000 0xa04d00
#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
@@ -537,6 +635,14 @@ enum iwm_secure_boot_status_reg {
#define IWM_SB_CPU_1_STATUS 0xa01e30
#define IWM_SB_CPU_2_STATUS 0Xa01e34
+#define IWM_UREG_CHICK 0xa05c00
+#define IWM_UREG_CHICK_MSI_ENABLE (1 << 24)
+#define IWM_UREG_CHICK_MSIX_ENABLE (1 << 25)
+
+#define IWM_HPM_DEBUG 0xa03440
+#define IWM_HPM_PERSISTENCE_BIT (1 << 12)
+#define IWM_PREG_WFPM_ACCESS (1 << 12)
+
/* Used to enable DBGM */
#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
@@ -562,25 +668,51 @@ enum iwm_secure_boot_status_reg {
#define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
#define IWM_HOST_INT_TIMEOUT_DEF (0x40)
#define IWM_HOST_INT_TIMEOUT_MIN (0x0)
-#define IWM_HOST_INT_OPER_MODE (1 << 31)
+#define IWM_HOST_INT_OPER_MODE (1U << 31)
/*****************************************************************************
* 7000/3000 series SHR DTS addresses *
*****************************************************************************/
/* Diode Results Register Structure: */
-enum iwm_dtd_diode_reg {
- IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
- IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
- IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
- IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
- IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
- IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
+#define IWM_DTS_DIODE_REG_DIG_VAL 0x000000FF /* bits [7:0] */
+#define IWM_DTS_DIODE_REG_VREF_LOW 0x0000FF00 /* bits [15:8] */
+#define IWM_DTS_DIODE_REG_VREF_HIGH 0x00FF0000 /* bits [23:16] */
+#define IWM_DTS_DIODE_REG_VREF_ID 0x03000000 /* bits [25:24] */
+#define IWM_DTS_DIODE_REG_PASS_ONCE 0x80000000 /* bits [31:31] */
+#define IWM_DTS_DIODE_REG_FLAGS_MSK 0xFF000000 /* bits [31:24] */
/* Those are the masks INSIDE the flags bit-field: */
- IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
- IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
- IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
- IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
+#define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS 0
+#define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID 0x00000003 /* bits [1:0] */
+#define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS 7
+#define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE 0x00000080 /* bits [7:7] */
+
+/*****************************************************************************
+ * MSIX related registers *
+ *****************************************************************************/
+
+#define IWM_CSR_MSIX_BASE (0x2000)
+#define IWM_CSR_MSIX_FH_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x800)
+#define IWM_CSR_MSIX_FH_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x804)
+#define IWM_CSR_MSIX_HW_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x808)
+#define IWM_CSR_MSIX_HW_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x80C)
+#define IWM_CSR_MSIX_AUTOMASK_ST_AD (IWM_CSR_MSIX_BASE + 0x810)
+#define IWM_CSR_MSIX_RX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x880)
+#define IWM_CSR_MSIX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x890)
+#define IWM_CSR_MSIX_PENDING_PBA_AD (IWM_CSR_MSIX_BASE + 0x1000)
+#define IWM_CSR_MSIX_RX_IVAR(cause) (IWM_CSR_MSIX_RX_IVAR_AD_REG + (cause))
+#define IWM_CSR_MSIX_IVAR(cause) (IWM_CSR_MSIX_IVAR_AD_REG + (cause))
+
+/*
+ * Causes for the FH register interrupts
+ */
+enum msix_fh_int_causes {
+ IWM_MSIX_FH_INT_CAUSES_Q0 = (1 << 0),
+ IWM_MSIX_FH_INT_CAUSES_Q1 = (1 << 1),
+ IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16),
+ IWM_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17),
+ IWM_MSIX_FH_INT_CAUSES_S2D = (1 << 19),
+ IWM_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21),
};
/*
@@ -591,13 +723,58 @@ enum iwm_dtd_diode_reg {
* BEGIN iwl-fw.h
*/
+/*
+ * Causes for the HW register interrupts
+ */
+enum msix_hw_int_causes {
+ IWM_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0),
+ IWM_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1),
+ IWM_MSIX_HW_INT_CAUSES_REG_IPC = (1 << 1),
+ IWM_MSIX_HW_INT_CAUSES_REG_IML = (1 << 2),
+ IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5),
+ IWM_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6),
+ IWM_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7),
+ IWM_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8),
+ IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25),
+ IWM_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26),
+ IWM_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27),
+ IWM_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29),
+ IWM_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30),
+};
+
+/*
+ * Registers to map causes to vectors
+ */
+enum msix_ivar_for_cause {
+ IWM_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0,
+ IWM_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1,
+ IWM_MSIX_IVAR_CAUSE_S2D = 0x3,
+ IWM_MSIX_IVAR_CAUSE_FH_ERR = 0x5,
+ IWM_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10,
+ IWM_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11,
+ IWM_MSIX_IVAR_CAUSE_REG_IML = 0x12,
+ IWM_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16,
+ IWM_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17,
+ IWM_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18,
+ IWM_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29,
+ IWM_MSIX_IVAR_CAUSE_REG_SCD = 0x2a,
+ IWM_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b,
+ IWM_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d,
+ IWM_MSIX_IVAR_CAUSE_REG_HAP = 0x2e,
+};
+
+#define IWM_MSIX_AUTO_CLEAR_CAUSE (0 << 7)
+#define IWM_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7)
+
/**
- * enum iwm_ucode_tlv_flag - ucode API flags
+ * uCode API flags
* @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
* was a separate TLV but moved here to save space.
* @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
* treats good CRC threshold as a boolean
* @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
+ * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
+ * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
* @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
* @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
* offload profile config command.
@@ -607,39 +784,48 @@ enum iwm_dtd_diode_reg {
* from the probe request template.
* @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
* @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
+ * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
+ * single bound interface).
* @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
* @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
* @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
* @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
+ * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
+ *
*/
-enum iwm_ucode_tlv_flag {
- IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
- IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
- IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
- IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
- IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
- IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
- IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
- IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
- IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
- IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25),
- IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
- IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29),
-};
+#define IWM_UCODE_TLV_FLAGS_PAN (1 << 0)
+#define IWM_UCODE_TLV_FLAGS_NEWSCAN (1 << 1)
+#define IWM_UCODE_TLV_FLAGS_MFP (1 << 2)
+#define IWM_UCODE_TLV_FLAGS_P2P (1 << 3)
+#define IWM_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4)
+#define IWM_UCODE_TLV_FLAGS_SHORT_BL (1 << 7)
+#define IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10)
+#define IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12)
+#define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15)
+#define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16)
+#define IWM_UCODE_TLV_FLAGS_P2P_PS (1 << 21)
+#define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22)
+#define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23)
+#define IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24)
+#define IWM_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25)
+#define IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26)
+#define IWM_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29)
+#define IWM_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30)
+#define IWM_UCODE_TLV_FLAGS_LTE_COEX (1U << 31)
#define IWM_UCODE_TLV_FLAG_BITS \
- "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \
-Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \
-L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \
-P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
+ "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
/**
- * enum iwm_ucode_tlv_api - ucode api
+ * uCode TLV api
* @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
* longer than the passive one, which is essential for fragmented scan.
* @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
+ * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
* @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
* @IWM_UCODE_TLV_API_NEW_VERSION: new versioning format
+ * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
+ * (command version 3) that supports per-chain limits
* @IWM_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan
* iteration complete notification, and the timestamp reported for RX
* received during scan, are reported in TSF of the mac specified in the
@@ -647,71 +833,35 @@ P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40L
* @IWM_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of
* ADD_MODIFY_STA_KEY_API_S_VER_2.
* @IWM_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement.
- * @IWM_UCODE_TLV_API_NAN2_VER2: This ucode supports NAN API version 2
+ * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
+ * instead of 3.
* @IWM_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used
- * @IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY: Quota command includes a field
- * indicating low latency direction.
- * @IWM_UCODE_TLV_API_DEPRECATE_TTAK: RX status flag TTAK ok (bit 7) is
- * deprecated.
- * @IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2: This ucode supports version 8
- * of scan request: SCAN_REQUEST_CMD_UMAC_API_S_VER_8
- * @IWM_UCODE_TLV_API_FRAG_EBS: This ucode supports fragmented EBS
- * @IWM_UCODE_TLV_API_REDUCE_TX_POWER: This ucode supports v5 of
- * the REDUCE_TX_POWER_CMD.
- * @IWM_UCODE_TLV_API_SHORT_BEACON_NOTIF: This ucode supports the short
- * version of the beacon notification.
- * @IWM_UCODE_TLV_API_BEACON_FILTER_V4: This ucode supports v4 of
- * BEACON_FILTER_CONFIG_API_S_VER_4.
- * @IWM_UCODE_TLV_API_REGULATORY_NVM_INFO: This ucode supports v4 of
- * REGULATORY_NVM_GET_INFO_RSP_API_S.
- * @IWM_UCODE_TLV_API_FTM_NEW_RANGE_REQ: This ucode supports v7 of
- * LOCATION_RANGE_REQ_CMD_API_S and v6 of LOCATION_RANGE_RESP_NTFY_API_S.
- * @IWM_UCODE_TLV_API_SCAN_OFFLOAD_CHANS: This ucode supports v2 of
- * SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S and v3 of
- * SCAN_OFFLOAD_PROFILES_QUERY_RSP_S.
- * @IWM_UCODE_TLV_API_MBSSID_HE: This ucode supports v2 of
- * STA_CONTEXT_DOT11AX_API_S
- * @IWM_UCODE_TLV_CAPA_SAR_TABLE_VER: This ucode supports different sar
- * version tables.
*
* @IWM_NUM_UCODE_TLV_API: number of bits used
*/
-enum iwm_ucode_tlv_api {
- IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8,
- IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9,
- IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18,
- IWM_UCODE_TLV_API_NEW_VERSION = 20,
- IWM_UCODE_TLV_API_SCAN_TSF_REPORT = 28,
- IWM_UCODE_TLV_API_TKIP_MIC_KEYS = 29,
- IWM_UCODE_TLV_API_STA_TYPE = 30,
- IWM_UCODE_TLV_API_NAN2_VER2 = 31,
- IWM_UCODE_TLV_API_ADAPTIVE_DWELL = 32,
- IWM_UCODE_TLV_API_OCE = 33,
- IWM_UCODE_TLV_API_NEW_BEACON_TEMPLATE = 34,
- IWM_UCODE_TLV_API_NEW_RX_STATS = 35,
- IWM_UCODE_TLV_API_WOWLAN_KEY_MATERIAL = 36,
- IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY = 38,
- IWM_UCODE_TLV_API_DEPRECATE_TTAK = 41,
- IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 = 42,
- IWM_UCODE_TLV_API_FRAG_EBS = 44,
- IWM_UCODE_TLV_API_REDUCE_TX_POWER = 45,
- IWM_UCODE_TLV_API_SHORT_BEACON_NOTIF = 46,
- IWM_UCODE_TLV_API_BEACON_FILTER_V4 = 47,
- IWM_UCODE_TLV_API_REGULATORY_NVM_INFO = 48,
- IWM_UCODE_TLV_API_FTM_NEW_RANGE_REQ = 49,
- IWM_UCODE_TLV_API_SCAN_OFFLOAD_CHANS = 50,
- IWM_UCODE_TLV_API_MBSSID_HE = 52,
- IWM_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE = 53,
- IWM_UCODE_TLV_API_FTM_RTT_ACCURACY = 54,
- IWM_UCODE_TLV_API_SAR_TABLE_VER = 55,
- IWM_UCODE_TLV_API_ADWELL_HB_DEF_N_AP = 57,
- IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER = 58,
-
- IWM_NUM_UCODE_TLV_API = 128,
-};
-
-/**
- * enum iwm_ucode_tlv_capa - ucode capabilities
+#define IWM_UCODE_TLV_API_FRAGMENTED_SCAN 8
+#define IWM_UCODE_TLV_API_WIFI_MCC_UPDATE 9
+#define IWM_UCODE_TLV_API_WIDE_CMD_HDR 14
+#define IWM_UCODE_TLV_API_LQ_SS_PARAMS 18
+#define IWM_UCODE_TLV_API_NEW_VERSION 20
+#define IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY 24
+#define IWM_UCODE_TLV_API_TX_POWER_CHAIN 27
+#define IWM_UCODE_TLV_API_SCAN_TSF_REPORT 28
+#define IWM_UCODE_TLV_API_TKIP_MIC_KEYS 29
+#define IWM_UCODE_TLV_API_STA_TYPE 30
+#define IWM_UCODE_TLV_API_NAN2_VER2 31
+#define IWM_UCODE_TLV_API_ADAPTIVE_DWELL 32
+#define IWM_UCODE_TLV_API_NEW_RX_STATS 35
+#define IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY 38
+#define IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42
+#define IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58
+#define IWM_NUM_UCODE_TLV_API 128
+
+#define IWM_UCODE_TLV_API_BITS \
+ "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS"
+
+/**
+ * uCode capabilities
* @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
* @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
* @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
@@ -763,55 +913,57 @@ enum iwm_ucode_tlv_api {
* @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
* memory addresses from the firmware.
* @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
- * @IWM_UCODE_TLV_CAPA_TX_POWER_ACK: reduced TX power API has larger
- * command size (command version 4) that supports toggling ACK TX
- * power reduction.
+ * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
+ * 0=no support)
*
* @IWM_NUM_UCODE_TLV_CAPA: number of bits used
*/
-enum iwm_ucode_tlv_capa {
- IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0,
- IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1,
- IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2,
- IWM_UCODE_TLV_CAPA_BEAMFORMER = 3,
- IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5,
- IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6,
- IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8,
- IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9,
- IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10,
- IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11,
- IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12,
- IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13,
- IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17,
- IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18,
- IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19,
- IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20,
- IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21,
- IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22,
- IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26,
- IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28,
- IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29,
- IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30,
- IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31,
- IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34,
- IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35,
- IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64,
- IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65,
- IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67,
- IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68,
- IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71,
- IWM_UCODE_TLV_CAPA_BEACON_STORING = 72,
- IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73,
- IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74,
- IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75,
- IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76,
- IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77,
- IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80,
- IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81,
- IWM_UCODE_TLV_CAPA_TX_POWER_ACK = 84,
-
- IWM_NUM_UCODE_TLV_CAPA = 128
-};
+#define IWM_UCODE_TLV_CAPA_D0I3_SUPPORT 0
+#define IWM_UCODE_TLV_CAPA_LAR_SUPPORT 1
+#define IWM_UCODE_TLV_CAPA_UMAC_SCAN 2
+#define IWM_UCODE_TLV_CAPA_BEAMFORMER 3
+#define IWM_UCODE_TLV_CAPA_TOF_SUPPORT 5
+#define IWM_UCODE_TLV_CAPA_TDLS_SUPPORT 6
+#define IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8
+#define IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9
+#define IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10
+#define IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11
+#define IWM_UCODE_TLV_CAPA_DQA_SUPPORT 12
+#define IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13
+#define IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17
+#define IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18
+#define IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19
+#define IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20
+#define IWM_UCODE_TLV_CAPA_CSUM_SUPPORT 21
+#define IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22
+#define IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26
+#define IWM_UCODE_TLV_CAPA_BT_COEX_PLCR 28
+#define IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC 29
+#define IWM_UCODE_TLV_CAPA_BT_COEX_RRC 30
+#define IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT 31
+#define IWM_UCODE_TLV_CAPA_NAN_SUPPORT 34
+#define IWM_UCODE_TLV_CAPA_UMAC_UPLOAD 35
+#define IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37
+#define IWM_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39
+#define IWM_UCODE_TLV_CAPA_CDB_SUPPORT 40
+#define IWM_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44
+#define IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48
+#define IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64
+#define IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65
+#define IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67
+#define IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68
+#define IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71
+#define IWM_UCODE_TLV_CAPA_BEACON_STORING 72
+#define IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 73
+#define IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW 74
+#define IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75
+#define IWM_UCODE_TLV_CAPA_CTDP_SUPPORT 76
+#define IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77
+#define IWM_UCODE_TLV_CAPA_LMAC_UPLOAD 79
+#define IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80
+#define IWM_UCODE_TLV_CAPA_LQM_SUPPORT 81
+
+#define IWM_NUM_UCODE_TLV_CAPA 128
/* The default calibrate table size if not specified by firmware file */
#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
@@ -821,17 +973,6 @@ enum iwm_ucode_tlv_capa {
/* The default max probe length if not specified by the firmware file */
#define IWM_DEFAULT_MAX_PROBE_LENGTH 200
*** 4208 LINES SKIPPED ***