git: be01656fa4cd - main - tegra124: Implement new get_gate method for tegra124 clocks.

The branch main has been updated by mmel:

URL: https://cgit.FreeBSD.org/src/commit/?id=be01656fa4cd78f191c0ad8a6f4640a0c520d5a9

commit be01656fa4cd78f191c0ad8a6f4640a0c520d5a9
Author:     Michal Meloun <mmel@FreeBSD.org>
AuthorDate: 2021-12-24 19:13:33 +0000
Commit:     Michal Meloun <mmel@FreeBSD.org>
CommitDate: 2021-12-24 19:16:24 +0000

    tegra124: Implement new get_gate method for tegra124 clocks.
    
    MFC after:      1 week
---
 sys/arm/nvidia/tegra124/tegra124_clk_per.c | 19 +++++++++++++++++++
 sys/arm/nvidia/tegra124/tegra124_clk_pll.c | 15 +++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/sys/arm/nvidia/tegra124/tegra124_clk_per.c b/sys/arm/nvidia/tegra124/tegra124_clk_per.c
index 4d68e8b22daf..b555a15786a4 100644
--- a/sys/arm/nvidia/tegra124/tegra124_clk_per.c
+++ b/sys/arm/nvidia/tegra124/tegra124_clk_per.c
@@ -697,6 +697,7 @@ periph_register(struct clkdom *clkdom, struct periph_def *clkdef)
 /* -------------------------------------------------------------------------- */
 static int pgate_init(struct clknode *clk, device_t dev);
 static int pgate_set_gate(struct clknode *clk, bool enable);
+static int pgate_get_gate(struct clknode *clk, bool *enableD);
 
 struct pgate_sc {
 	device_t		clkdev;
@@ -710,6 +711,7 @@ static clknode_method_t pgate_methods[] = {
 	/* Device interface */
 	CLKNODEMETHOD(clknode_init,		pgate_init),
 	CLKNODEMETHOD(clknode_set_gate,		pgate_set_gate),
+	CLKNODEMETHOD(clknode_get_gate,		pgate_get_gate),
 	CLKNODEMETHOD_END
 };
 DEFINE_CLASS_1(tegra124_pgate, tegra124_pgate_class, pgate_methods,
@@ -771,6 +773,23 @@ pgate_set_gate(struct clknode *clk, bool enable)
 	return(0);
 }
 
+static int
+pgate_get_gate(struct clknode *clk, bool *enabled)
+{
+	struct pgate_sc *sc;
+	uint32_t reg, mask, base_reg;
+
+	sc = clknode_get_softc(clk);
+	mask = 1 << (sc->idx % 32);
+	base_reg = get_enable_reg(sc->idx);
+
+	DEVICE_LOCK(sc);
+	RD4(sc, base_reg, &reg);
+	DEVICE_UNLOCK(sc);
+	*enabled = reg & mask ? true: false;
+
+	return(0);
+}
 int
 tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, bool reset)
 {
diff --git a/sys/arm/nvidia/tegra124/tegra124_clk_pll.c b/sys/arm/nvidia/tegra124/tegra124_clk_pll.c
index 82b34fd71203..d6aa55f8efe0 100644
--- a/sys/arm/nvidia/tegra124/tegra124_clk_pll.c
+++ b/sys/arm/nvidia/tegra124/tegra124_clk_pll.c
@@ -382,6 +382,7 @@ static struct clk_pll_def pll_clks[] = {
 
 static int tegra124_pll_init(struct clknode *clk, device_t dev);
 static int tegra124_pll_set_gate(struct clknode *clk, bool enable);
+static int tegra124_pll_get_gate(struct clknode *clk, bool *enabled);
 static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq);
 static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin,
     uint64_t *fout, int flags, int *stop);
@@ -403,6 +404,7 @@ static clknode_method_t tegra124_pll_methods[] = {
 	/* Device interface */
 	CLKNODEMETHOD(clknode_init,		tegra124_pll_init),
 	CLKNODEMETHOD(clknode_set_gate,		tegra124_pll_set_gate),
+	CLKNODEMETHOD(clknode_get_gate,		tegra124_pll_get_gate),
 	CLKNODEMETHOD(clknode_recalc_freq,	tegra124_pll_recalc),
 	CLKNODEMETHOD(clknode_set_freq,		tegra124_pll_set_freq),
 	CLKNODEMETHOD_END
@@ -688,6 +690,19 @@ tegra124_pll_set_gate(struct clknode *clknode, bool enable)
 	return (rv);
 }
 
+static int
+tegra124_pll_get_gate(struct clknode *clknode, bool *enabled)
+{
+	uint32_t reg;
+	struct pll_sc *sc;
+
+	sc = clknode_get_softc(clknode);
+	RD4(sc, sc->base_reg, &reg);
+	*enabled = reg & PLL_BASE_ENABLE ? true: false;
+	WR4(sc, sc->base_reg, reg);
+	return (0);
+}
+
 static int
 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
     uint32_t m, uint32_t n, uint32_t p)