From nobody Mon Dec 20 10:41:43 2021 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 0D3FB18F691D; Mon, 20 Dec 2021 10:41:44 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4JHbjz5hQpz4TpC; Mon, 20 Dec 2021 10:41:43 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id A349014BB6; Mon, 20 Dec 2021 10:41:43 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 1BKAfhfc069778; Mon, 20 Dec 2021 10:41:43 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 1BKAfhBi069777; Mon, 20 Dec 2021 10:41:43 GMT (envelope-from git) Date: Mon, 20 Dec 2021 10:41:43 GMT Message-Id: <202112201041.1BKAfhBi069777@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andriy Gapon Subject: git: 08ff54dc5b5d - main - aw_spi: improve I/O stability List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-main@freebsd.org X-BeenThere: dev-commits-src-main@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: avg X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 08ff54dc5b5de85580044167e1714fb75df8e44f Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1639996903; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Pj+kigbUue8ScZHoCON3GgGcofx4Jwbih7zvjGd7BNE=; b=kascoyTg1uAdrE5TWQiqTabHSxZrUhwmqe/vlUc9V5d4imo877gJA5zOKAvUvo9+LgUl+R 8Q81me215PXoKrpOSZ45oKPodPMN+Bvvcps/RStbcNPOzMQm38vB3rCPClVHt6lm+hHnbq 7Aj+USM2dRW2nPx28kPX6bTC7Bgt8ORIGDBxDe0DzWqyrwahH37IUrZWXrKRm9+1WY9Lfh qxsUAsowC3cK96OCQxOVAi+PZwRp/wkf9kXEJkYfAstqAX/BNTLzwDh1DAaxU/VrN6pWTG 1r0QsqK0IP2nZgPdkrfDkjbW734VFpauI/RMK2ch76pbeSeeL2AbzEpcMetrBw== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1639996903; a=rsa-sha256; cv=none; b=xdF+4khAmSJOh31qZzCsXRLxW060YkiBNGpeibwUZXewzOVVm9TP0qCRre0VnfL8LlMbpC Oip9+NqhMHF9M1QBOwj0GSsHhf4ik3a/Aan1R++lWr84yAEWKWWPIHYOqYYPtYYakU8MGa NL2mCjghSc9YRQbjMdiZ5QpVbRf4vojeRde6m4XDiaITff9THSSnSTmJx5UU+c8UHUjXLS vdtAay1VV3IgUq1zJkEGtzaRDurT2alXt0RtC7sCyoD3zqYJObxXWN8akUI5RQ75d/qX3W OGouGNNQ3ArVJW558Hm9Em66Twmheadifj7NX3yoO85GyOTP16nzBgISujboOg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by avg: URL: https://cgit.FreeBSD.org/src/commit/?id=08ff54dc5b5de85580044167e1714fb75df8e44f commit 08ff54dc5b5de85580044167e1714fb75df8e44f Author: Andriy Gapon AuthorDate: 2021-12-20 10:40:17 +0000 Commit: Andriy Gapon CommitDate: 2021-12-20 10:40:17 +0000 aw_spi: improve I/O stability This driver does not use DMA at the moment, so some care is needed to prevent TX FIFO underruns and RX FIFO overflows. Several improvements are done in oder to minimize chances of those. First, the interrupt handling is moved to a filter to minimize latency. Second, FIFO trigger thresholds are configured for both FIFOs. The TX FIFO threshold is set to 3/4-th of its size and the RX FIFO threshold is set to 1/4-th of its size. The interrupt conditions are changed from the empty FIFO and full FIFO for the TX and RX correspondingly to going below and above the thresholds. While here I renamed AW_SPI_IER_RF_ERQ to AW_SPI_IER_RF_RDY which is closer to what the documentation uses, RF_RDY_INT_EN in the interrupt control register and RX_RDY in the interrupt status register. Reviewed by: manu MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D33558 --- sys/arm/allwinner/aw_spi.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/sys/arm/allwinner/aw_spi.c b/sys/arm/allwinner/aw_spi.c index 0952102575b3..0f5cee8769de 100644 --- a/sys/arm/allwinner/aw_spi.c +++ b/sys/arm/allwinner/aw_spi.c @@ -84,7 +84,7 @@ __FBSDID("$FreeBSD$"); #define AW_SPI_IER_TF_ERQ (1 << 4) /* TXFIFO Empty Request */ #define AW_SPI_IER_RF_FULL (1 << 2) /* RXFIFO Full */ #define AW_SPI_IER_RF_EMP (1 << 1) /* RXFIFO Empty */ -#define AW_SPI_IER_RF_ERQ (1 << 0) /* RXFIFO Empty Request */ +#define AW_SPI_IER_RF_RDY (1 << 0) /* RXFIFO Ready Request */ #define AW_SPI_ISR 0x14 /* Interrupt Status Register */ @@ -169,7 +169,7 @@ struct aw_spi_softc { static int aw_spi_probe(device_t dev); static int aw_spi_attach(device_t dev); static int aw_spi_detach(device_t dev); -static void aw_spi_intr(void *arg); +static int aw_spi_intr(void *arg); static int aw_spi_probe(device_t dev) @@ -202,7 +202,7 @@ aw_spi_attach(device_t dev) } if (bus_setup_intr(dev, sc->res[1], - INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_spi_intr, sc, + INTR_TYPE_MISC | INTR_MPSAFE, aw_spi_intr, NULL, sc, &sc->intrhand)) { bus_release_resources(dev, aw_spi_spec, sc->res); device_printf(dev, "cannot setup interrupt handler\n"); @@ -424,7 +424,7 @@ aw_spi_read_rxfifo(struct aw_spi_softc *sc) } } -static void +static int aw_spi_intr(void *arg) { struct aw_spi_softc *sc; @@ -434,18 +434,19 @@ aw_spi_intr(void *arg) intr = AW_SPI_READ_4(sc, AW_SPI_ISR); - if (intr & AW_SPI_IER_RF_FULL) + if (intr & AW_SPI_IER_RF_RDY) aw_spi_read_rxfifo(sc); - if (intr & AW_SPI_IER_TF_EMP) { + if (intr & AW_SPI_IER_TF_ERQ) { aw_spi_fill_txfifo(sc); - /* - * If we don't have anything else to write + + /* + * If we don't have anything else to write * disable TXFifo interrupts */ if (sc->txcnt == sc->txlen) AW_SPI_WRITE_4(sc, AW_SPI_IER, AW_SPI_IER_TC | - AW_SPI_IER_RF_FULL); + AW_SPI_IER_RF_RDY); } if (intr & AW_SPI_IER_TC) { @@ -460,6 +461,7 @@ aw_spi_intr(void *arg) /* Clear Interrupts */ AW_SPI_WRITE_4(sc, AW_SPI_ISR, intr); + return (intr != 0 ? FILTER_HANDLED : FILTER_STRAY); } static int @@ -488,6 +490,14 @@ aw_spi_xfer(struct aw_spi_softc *sc, void *rxbuf, void *txbuf, uint32_t txlen, u return (EIO); } + /* + * Set the TX FIFO threshold to 3/4-th the size and + * the RX FIFO one to 1/4-th. + */ + AW_SPI_WRITE_4(sc, AW_SPI_FCR, + ((3 * AW_SPI_FIFO_SIZE / 4) << AW_SPI_FCR_TX_TRIG_SHIFT) | + ((AW_SPI_FIFO_SIZE / 4) << AW_SPI_FCR_RX_TRIG_SHIFT)); + /* Write the counters */ AW_SPI_WRITE_4(sc, AW_SPI_MBC, txlen); AW_SPI_WRITE_4(sc, AW_SPI_MTC, txlen); @@ -501,14 +511,14 @@ aw_spi_xfer(struct aw_spi_softc *sc, void *rxbuf, void *txbuf, uint32_t txlen, u reg |= AW_SPI_TCR_XCH; AW_SPI_WRITE_4(sc, AW_SPI_TCR, reg); - /* + /* * Enable interrupts for : * Transmit complete - * TX Fifo empty - * RX Fifo full + * TX Fifo is below its trigger threshold + * RX Fifo is above its trigger threshold */ AW_SPI_WRITE_4(sc, AW_SPI_IER, AW_SPI_IER_TC | - AW_SPI_IER_TF_EMP | AW_SPI_IER_RF_FULL); + AW_SPI_IER_TF_ERQ | AW_SPI_IER_RF_RDY); sc->transfer = 1;