git: ccaeaa843055 - stable/15 - amd64/pmap: Return la57 in amd nested page

The branch stable/15 has been updated by markj:

URL: https://cgit.FreeBSD.org/src/commit/?id=ccaeaa843055442fd73020f6efce2a23fdfc0e84

commit ccaeaa843055442fd73020f6efce2a23fdfc0e84
Author:     ShengYi Hung <aokblast@FreeBSD.org>
AuthorDate: 2026-09-11 08:22:39 +0000
Commit:     Mark Johnston <markj@FreeBSD.org>
CommitDate: 2026-09-22 17:06:52 +0000

    amd64/pmap: Return la57 in amd nested page
    
    AMD doesn't encode page depth in eptp. As a result, the page level is
    decided by the host la57 value. Without this, it uses 4 level page and
    therefore cause machine enable la57 have garbage page translation.
    
    PR:             291768
    Reviewed by:    kib
    Tested by:      Antranig Vartanian <antranigv@freebsd.am>
    MFC after:      1 week
    Differential Revision:  https://reviews.freebsd.org/D57978
    
    (cherry picked from commit ef26f64c11220ea303de16d088c585f9d2908b0f)
---
 sys/amd64/amd64/pmap.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/sys/amd64/amd64/pmap.c b/sys/amd64/amd64/pmap.c
index 497c85c3f0c2..63ff6269119b 100644
--- a/sys/amd64/amd64/pmap.c
+++ b/sys/amd64/amd64/pmap.c
@@ -443,7 +443,19 @@ pmap_is_la57(pmap_t pmap)
 {
 	if (pmap->pm_type == PT_X86)
 		return (la57);
-	return (false);		/* XXXKIB handle EPT */
+	if (pmap->pm_type == PT_RVI) {
+		/*
+		 * AMD nested paging has no field to specify the nested
+		 * page table walk length; the hardware derives it from
+		 * the host CR4.LA57 setting (see svm.c, where nCR3 is
+		 * loaded directly from pm_pmltop with no level encoding).
+		 * The NPT must therefore have the same number of levels
+		 * as the host page tables, otherwise guest-physical
+		 * translations are walked at the wrong depth.
+		 */
+		return (la57);
+	}
+	return (false);		/* Intel EPT encodes its own walk length. */
 }
 
 #define	PAT_INDEX_SIZE	8