From nobody Mon Sep 07 07:24:06 2026 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4hddqB52nPz6rbrr for ; Mon, 07 Sep 2026 07:24:06 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4hddqB4LYTz3s2W for ; Mon, 07 Sep 2026 07:24:06 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1788765846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=3QDb1jpRBzrNcBMf3cIItMrOJIJmD9diWxzr/dui0HM=; b=SMX79RR6f3ItaWtte6VbShQfxJJsZEaXrPPtS34Ch9to3KI4bKc9ejv5o1BEYPQjzAXYaD D7eO1Zf5Z01AfTaoIDtBSwtlzqTvMAz0B802VIIxxw6JIng3U90qmHx06s60LD3wrkrGnM UBtZ2VUD0Lb0DQBQ9tKBeqBg78PZlq15Q8Zq6d7/OmukanqR9dc9jbHneVGRmJ+q68wGvy 1J888r0DVF9bpz9B6TQJCOnVnl97Lqgq4cTmpLzTYDETtIxC9P3ElrugCnAbwou+bz9Ijo yLgISc34jFO9LHlsDH379Va8DoybTlZbsZ8wnkJdJXsb/UG/SQVEW2f/2VYHcg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1788765846; a=rsa-sha256; cv=none; b=p9vAusC0OkhU/IwJv10WsdqBNbg7UZ6xp+r2f08UtVuXvHJMNutlqCZZQFzpa1yfMf8nVO nRxnDbfpeWBQCbuowlm4C+NF9DdCJzBI2lOzmLM2AG7A2CLG3htkkOID4ybtqM6fBR3VrZ RkhLMu00JjiaH2C/SOgccaYnCgFuEj2VZlN4w8nTCORaO/fmzhBoRXzn4vA/FQIGHKXS+W h+r4s5qNOFBJIvQRl5KxDP+9muvfviUuQLEvQpAXpk3JKZVhF6cx9UVAhxgfwQlNrwy4uR 8jF7indlZwgS9W5sA084XNXcPgOI4kikOaxl9eWGmeRsnTKU9vploKtckab1wQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1788765846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=3QDb1jpRBzrNcBMf3cIItMrOJIJmD9diWxzr/dui0HM=; b=JDUhlEwb/mQfBQ1IBSp4ts0py3t3fQVxNGz+tlNlIM3bHtzW7FeIyQXcS9u6u8NECkcuAo RAcvRblG4cyBPRRgH+AHAJQbK7BNnGY6erSOIC1cBD6KW6PbOoLC3sp/qYCjFdYuUt22Xc 6dDpvMVa6TKxr2Bsj7TtlxRFmV6XSowBI9g2H7fInzkRz+qfYQUU1BYEG/MxIJ7nQjKi9a 9Jp9lU7C1BFuscyrzqt1/oA14FedrldNOjB/qd3t7yQ4BGWdDcxOD2hHKpmErd3CMqM4qw I9Jisv6cgXvZKNLErAvEdj3ScMkHuDY44XaXPwYKJ40yIQkIZyFV9T0/NgwpIg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4hddqB2wSDz170J for ; Mon, 07 Sep 2026 07:24:06 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 37f92 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Mon, 07 Sep 2026 07:24:06 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Kevin Bowling Subject: git: 1cc8353a1c63 - stable/14 - e1000: Serialize 82579 CSR writes with the Management Engine List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-branches@freebsd.org Sender: owner-dev-commits-src-branches@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: kbowling X-Git-Repository: src X-Git-Refname: refs/heads/stable/14 X-Git-Reftype: branch X-Git-Commit: 1cc8353a1c633aedc6f4a7af198fddcc26a63126 Auto-Submitted: auto-generated Date: Mon, 07 Sep 2026 07:24:06 +0000 Message-Id: <6a9e6696.37f92.40bd5540@gitrepo.freebsd.org> The branch stable/14 has been updated by kbowling: URL: https://cgit.FreeBSD.org/src/commit/?id=1cc8353a1c633aedc6f4a7af198fddcc26a63126 commit 1cc8353a1c633aedc6f4a7af198fddcc26a63126 Author: Kevin Bowling AuthorDate: 2026-08-16 07:10:09 +0000 Commit: Kevin Bowling CommitDate: 2026-09-07 07:23:13 +0000 e1000: Serialize 82579 CSR writes with the Management Engine The 82579 PCIm2PCI arbiter can acknowledge a host MAC CSR write while the Management Engine is accessing another CSR. The host write can be lost; subsequent target accesses may no longer be claimed by the MAC and can hang the system. For 82579 controllers with valid management firmware, wait for the ME CSR access indication before every MAC CSR write. Keep the wait bounded and use DELAY because writes occur in interrupt and datapath contexts. Verify every transmit and receive tail write. If a tail does not hold the requested value, disable its datapath direction and request a full iflib reset. Keep the ordinary register-write path as a direct MMIO write behind a predicted per-device gate. Contain the wait and tail recovery in the 82579 slow path rather than adding tail-specific accessors and state to the rest of the e1000 family. Documentation on the PCH NICs is scare so Intel's Linux e1000e fixes publicly document the hardware failure and required serialization as commits bdc125f73f3c and d601afcae2fe. This implementation is a bit cleaner. Tested on a Thinkpad T430 (82579LM) with a test kernel to simulate ME contention without incident as well as lost tail writes causing a succesful recovery. Sponsored by: BBOX.io (cherry picked from commit e7aa5a5a3f690f49488f89e01444ba1bcebc427b) --- sys/dev/e1000/e1000_osdep.c | 60 +++++++++++++++++++++++++++++++++++++++++++++ sys/dev/e1000/e1000_osdep.h | 20 +++++++++------ sys/dev/e1000/if_em.c | 9 +++++++ 3 files changed, 82 insertions(+), 7 deletions(-) diff --git a/sys/dev/e1000/e1000_osdep.c b/sys/dev/e1000/e1000_osdep.c index 8b598f18cf12..c38e963f2ea3 100644 --- a/sys/dev/e1000/e1000_osdep.c +++ b/sys/dev/e1000/e1000_osdep.c @@ -36,6 +36,66 @@ int e1000_use_pause_delay = 0; +/* + * Wait while the 82579 Management Engine owns the PCIm2PCI arbiter. DELAY + * is required because CSR writes also occur from interrupt and datapath + * contexts where sleeping is forbidden. + */ +static void +e1000_pcim2pci_arbiter_wait(struct e1000_osdep *osdep) +{ + int i; + + i = E1000_ICH_FWSM_PCIM2PCI_COUNT; + while ((bus_space_read_4(osdep->mem_bus_space_tag, + osdep->mem_bus_space_handle, E1000_FWSM) & + E1000_ICH_FWSM_PCIM2PCI) != 0 && --i != 0) + DELAY(50); +} + +/* + * Serialize an 82579 MAC CSR write against the Management Engine. The + * FreeBSD driver exposes one queue on this controller, so recognize its two + * tail registers here and verify them without imposing tail-specific APIs on + * the rest of the e1000 family. + */ +void +e1000_pcim2pci_write(struct e1000_osdep *osdep, uint32_t reg, uint32_t value) +{ + uint32_t control, control_reg, enable; + const char *direction; + + e1000_pcim2pci_arbiter_wait(osdep); + bus_space_write_4(osdep->mem_bus_space_tag, + osdep->mem_bus_space_handle, reg, value); + + if (reg == E1000_TDT(0)) { + control_reg = E1000_TCTL; + enable = E1000_TCTL_EN; + direction = "transmit"; + } else if (reg == E1000_RDT(0)) { + control_reg = E1000_RCTL; + enable = E1000_RCTL_EN; + direction = "receive"; + } else { + return; + } + if (bus_space_read_4(osdep->mem_bus_space_tag, + osdep->mem_bus_space_handle, reg) == value) + return; + + control = bus_space_read_4(osdep->mem_bus_space_tag, + osdep->mem_bus_space_handle, control_reg); + e1000_pcim2pci_arbiter_wait(osdep); + bus_space_write_4(osdep->mem_bus_space_tag, + osdep->mem_bus_space_handle, control_reg, control & ~enable); + device_printf(osdep->dev, + "Management Engine caused an invalid %s tail write; " + "requesting reset\n", direction); + iflib_request_reset(osdep->ctx); + iflib_admin_intr_deferred(osdep->ctx); +} + static void e1000_enable_pause_delay(void *use_pause_delay) { diff --git a/sys/dev/e1000/e1000_osdep.h b/sys/dev/e1000/e1000_osdep.h index ba1c8a16fad1..bac71d34de45 100644 --- a/sys/dev/e1000/e1000_osdep.h +++ b/sys/dev/e1000/e1000_osdep.h @@ -161,8 +161,11 @@ struct e1000_osdep bus_space_handle_t flash_bus_space_handle; device_t dev; if_ctx_t ctx; + bool pcim2pci_arbiter_wa; }; +void e1000_pcim2pci_write(struct e1000_osdep *, uint32_t, uint32_t); + #define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \ ? reg : e1000_translate_register_82542(reg)) @@ -173,11 +176,6 @@ struct e1000_osdep bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset) -/* Write to an absolute offset in the adapter's memory space */ -#define E1000_WRITE_OFFSET(hw, offset, value) \ - bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ - ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset, value) - static __inline uint32_t e1000_rd32(struct e1000_osdep *osdep, uint32_t reg) { @@ -199,10 +197,18 @@ e1000_wr32(struct e1000_osdep *osdep, uint32_t reg, uint32_t value) ("e1000: register offset %#jx too large (max is %#jx)", (uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size)); - bus_space_write_4(osdep->mem_bus_space_tag, - osdep->mem_bus_space_handle, reg, value); + if (__predict_true(!osdep->pcim2pci_arbiter_wa)) { + bus_space_write_4(osdep->mem_bus_space_tag, + osdep->mem_bus_space_handle, reg, value); + return; + } + e1000_pcim2pci_write(osdep, reg, value); } +/* Write to an absolute offset in the adapter's memory space. */ +#define E1000_WRITE_OFFSET(hw, offset, value) \ + e1000_wr32((hw)->back, (offset), (value)) + /* Register READ/WRITE macros */ #define E1000_READ_REG(hw, reg) \ diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index 832d969e98fc..f6d5d748650a 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -1176,6 +1176,15 @@ em_if_attach_pre(if_ctx_t ctx) error = ENXIO; goto err_pci; } + /* + * 82579 can lose a host CSR write while the Management Engine owns + * the PCIm2PCI arbiter. Enable the OS register write interlock before + * shared code initialization performs any MAC writes. + */ + if (hw->mac.type == e1000_pch2lan && + (E1000_READ_REG(hw, E1000_FWSM) & + E1000_ICH_FWSM_FW_VALID) != 0) + sc->osdep.pcim2pci_arbiter_wa = true; /* ** For ICH8 and family we need to