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charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: 66fb43c26b3ba9a86335f462ddb6e06b27323823 Auto-Submitted: auto-generated Date: Thu, 03 Sep 2026 16:29:55 +0000 Message-Id: <6a99a083.3937c.2f4387b6@gitrepo.freebsd.org> The branch stable/15 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=66fb43c26b3ba9a86335f462ddb6e06b27323823 commit 66fb43c26b3ba9a86335f462ddb6e06b27323823 Author: Mitchell Horne AuthorDate: 2025-08-10 17:13:23 +0000 Commit: Mitchell Horne CommitDate: 2026-09-03 16:29:00 +0000 jh7110_gpio: style - Fix whitespace - Replace JH7110_GPIO_READ with RD4 (and WR4) - Trim headers - Explicit conditional checks - Use correct method typedefs MFC after: 3 days Sponsored by: The FreeBSD Foundation (cherry picked from commit 72216145d3e4e2460d48d279a339072e0be2cc74) --- sys/riscv/starfive/jh7110_gpio.c | 101 +++++++++++++++++++-------------------- 1 file changed, 49 insertions(+), 52 deletions(-) diff --git a/sys/riscv/starfive/jh7110_gpio.c b/sys/riscv/starfive/jh7110_gpio.c index 1ed7d9f42259..96b2cef43a4c 100644 --- a/sys/riscv/starfive/jh7110_gpio.c +++ b/sys/riscv/starfive/jh7110_gpio.c @@ -4,12 +4,9 @@ * Copyright (c) 2023 Jari Sihvola */ -#include - #include #include #include - #include #include #include @@ -28,26 +25,26 @@ #include "gpio_if.h" -#define GPIO_PINS 64 -#define GPIO_REGS 2 +#define GPIO_PINS 64 +#define GPIO_REGS 2 -#define GP0_DOEN_CFG 0x0 -#define GP0_DOUT_CFG 0x40 -#define GPIOEN 0xdc -#define GPIOE_0 0x100 -#define GPIOE_1 0x104 -#define GPIO_DIN_LOW 0x118 -#define GPIO_DIN_HIGH 0x11c -#define IOMUX_SYSCFG_288 0x120 +#define GP0_DOEN_CFG 0x0 +#define GP0_DOUT_CFG 0x40 +#define GPIOEN 0xdc +#define GPIOE_0 0x100 +#define GPIOE_1 0x104 +#define GPIO_DIN_LOW 0x118 +#define GPIO_DIN_HIGH 0x11c +#define IOMUX_SYSCFG_288 0x120 -#define PAD_INPUT_EN (1 << 0) -#define PAD_PULLUP (1 << 3) -#define PAD_PULLDOWN (1 << 4) -#define PAD_HYST (1 << 6) +#define PAD_INPUT_EN (1 << 0) +#define PAD_PULLUP (1 << 3) +#define PAD_PULLDOWN (1 << 4) +#define PAD_HYST (1 << 6) -#define ENABLE_MASK 0x3f -#define DATA_OUT_MASK 0x7f -#define DIROUT_DISABLE 1 +#define ENABLE_MASK 0x3f +#define DATA_OUT_MASK 0x7f +#define DIROUT_DISABLE 1 struct jh7110_gpio_softc { device_t dev; @@ -67,15 +64,15 @@ static struct resource_spec jh7110_gpio_spec[] = { { -1, 0 } }; -#define GPIO_RW_OFFSET(_val) (_val & ~3) -#define GPIO_SHIFT(_val) ((_val & 3) * 8) -#define PAD_OFFSET(_val) (_val * 4) +#define GPIO_RW_OFFSET(_val) (_val & ~3) +#define GPIO_SHIFT(_val) ((_val & 3) * 8) +#define PAD_OFFSET(_val) (_val * 4) -#define JH7110_GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx) -#define JH7110_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) +#define JH7110_GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx) +#define JH7110_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) -#define JH7110_GPIO_READ(sc, reg) bus_read_4((sc)->res, (reg)) -#define JH7110_GPIO_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) +#define RD4(sc, reg) bus_read_4((sc)->res, (reg)) +#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) static device_t jh7110_gpio_get_bus(device_t dev) @@ -96,7 +93,7 @@ jh7110_gpio_pin_max(device_t dev, int *maxpin) } static int -jh7110_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) +jh7110_gpio_pin_get(device_t dev, uint32_t pin, uint32_t *val) { struct jh7110_gpio_softc *sc; uint32_t reg; @@ -108,10 +105,10 @@ jh7110_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) JH7110_GPIO_LOCK(sc); if (pin < GPIO_PINS / GPIO_REGS) { - reg = JH7110_GPIO_READ(sc, GPIO_DIN_LOW); + reg = RD4(sc, GPIO_DIN_LOW); *val = (reg >> pin) & 0x1; } else { - reg = JH7110_GPIO_READ(sc, GPIO_DIN_HIGH); + reg = RD4(sc, GPIO_DIN_HIGH); *val = (reg >> (pin - GPIO_PINS / GPIO_REGS)) & 0x1; } JH7110_GPIO_UNLOCK(sc); @@ -120,7 +117,7 @@ jh7110_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) } static int -jh7110_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) +jh7110_gpio_pin_set(device_t dev, uint32_t pin, uint32_t val) { struct jh7110_gpio_softc *sc; uint32_t reg; @@ -131,11 +128,11 @@ jh7110_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) return (EINVAL); JH7110_GPIO_LOCK(sc); - reg = JH7110_GPIO_READ(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin)); + reg = RD4(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin)); reg &= ~(DATA_OUT_MASK << GPIO_SHIFT(pin)); - if (value) + if (val != 0) reg |= 0x1 << GPIO_SHIFT(pin); - JH7110_GPIO_WRITE(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin), reg); + WR4(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin), reg); JH7110_GPIO_UNLOCK(sc); return (0); @@ -153,14 +150,14 @@ jh7110_gpio_pin_toggle(device_t dev, uint32_t pin) return (EINVAL); JH7110_GPIO_LOCK(sc); - reg = JH7110_GPIO_READ(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin)); - if (reg & 0x1 << GPIO_SHIFT(pin)) { + reg = RD4(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin)); + if ((reg & 0x1 << GPIO_SHIFT(pin)) != 0) { reg &= ~(DATA_OUT_MASK << GPIO_SHIFT(pin)); } else { reg &= ~(DATA_OUT_MASK << GPIO_SHIFT(pin)); reg |= 0x1 << GPIO_SHIFT(pin); } - JH7110_GPIO_WRITE(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin), reg); + WR4(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin), reg); JH7110_GPIO_UNLOCK(sc); return (0); @@ -201,7 +198,7 @@ jh7110_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) /* Reading the direction */ JH7110_GPIO_LOCK(sc); - reg = JH7110_GPIO_READ(sc, GP0_DOEN_CFG + GPIO_RW_OFFSET(pin)); + reg = RD4(sc, GP0_DOEN_CFG + GPIO_RW_OFFSET(pin)); if ((reg & ENABLE_MASK << GPIO_SHIFT(pin)) == 0) *flags |= GPIO_PIN_OUTPUT; else @@ -226,28 +223,28 @@ jh7110_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) JH7110_GPIO_LOCK(sc); - if (flags & GPIO_PIN_INPUT) { - reg = JH7110_GPIO_READ(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin)); + if ((flags & GPIO_PIN_INPUT) != 0) { + reg = RD4(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin)); reg |= (PAD_INPUT_EN | PAD_HYST); - JH7110_GPIO_WRITE(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin), reg); + WR4(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin), reg); } - reg = JH7110_GPIO_READ(sc, GP0_DOEN_CFG + GPIO_RW_OFFSET(pin)); + reg = RD4(sc, GP0_DOEN_CFG + GPIO_RW_OFFSET(pin)); reg &= ~(ENABLE_MASK << GPIO_SHIFT(pin)); - if (flags & GPIO_PIN_INPUT) { + if ((flags & GPIO_PIN_INPUT) != 0) { reg |= DIROUT_DISABLE << GPIO_SHIFT(pin); } - JH7110_GPIO_WRITE(sc, GP0_DOEN_CFG + GPIO_RW_OFFSET(pin), reg); + WR4(sc, GP0_DOEN_CFG + GPIO_RW_OFFSET(pin), reg); - if (flags & GPIO_PIN_OUTPUT) { - reg = JH7110_GPIO_READ(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin)); + if ((flags & GPIO_PIN_OUTPUT) != 0) { + reg = RD4(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin)); reg &= ~(ENABLE_MASK << GPIO_SHIFT(pin)); reg |= 0x1 << GPIO_SHIFT(pin); - JH7110_GPIO_WRITE(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin), reg); + WR4(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin), reg); - reg = JH7110_GPIO_READ(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin)); + reg = RD4(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin)); reg &= ~(PAD_INPUT_EN | PAD_PULLUP | PAD_PULLDOWN | PAD_HYST); - JH7110_GPIO_WRITE(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin), reg); + WR4(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin), reg); } JH7110_GPIO_UNLOCK(sc); @@ -317,9 +314,9 @@ jh7110_gpio_attach(device_t dev) } /* Reseting GPIO interrupts */ - JH7110_GPIO_WRITE(sc, GPIOE_0, 0); - JH7110_GPIO_WRITE(sc, GPIOE_1, 0); - JH7110_GPIO_WRITE(sc, GPIOEN, 1); + WR4(sc, GPIOE_0, 0); + WR4(sc, GPIOE_1, 0); + WR4(sc, GPIOEN, 1); sc->busdev = gpiobus_add_bus(dev); if (sc->busdev == NULL) {