From nobody Mon Oct 12 15:28:55 2026 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4j3LwS0fZrz6vxVr for ; Mon, 12 Oct 2026 15:28:56 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4j3LwR6Xktz3PNM for ; Mon, 12 Oct 2026 15:28:55 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791818935; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=j6ocoj/V6aJbXmR4Qm5OFIzA63NiP+fHWiuj303zuQA=; b=gbyag7ejTkanZoEeGG5yWfvoTFy9S0NFG9UW/98deqU0ED4p4BMsH7K7tjIuXTH6mNq4mZ +7rsoluByAmCHUPIMzzxMqSpNpVOYB9LEt+iQLizOnw2hf1YBbjVgMJ9LpxapPU1aG+vhc +qy9HoKr4UDDQ/uQjTprpiUfExpbOg8YtsJXLDz/xl4vsykvzGbHZ402o+hGGP9pr6a/1/ AZWTYl+jbDFIQGFaN/c1/9JgEzYTeNnJ6s9KaWTQK/tai8New0wOTTISeKIInlJomj8ayf 0LDDv1FnLpm/lGRz8sT9je46AnUyTuvhJWL6c8xdGs6+ciwc2pD8lPWkZP2s8Q== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1791818935; b=ZmPmixlkDXoSNHaLtgkoyLaSqMNkizy/2QzXkepqOUS5CIRFL8Or/40tDhcW8N/7Vj5+Uw zcoUBKWUALcjkGL7+5FC32pbJwCCHFqkOQAIxYD0KtF0W3wsUlKqMVbxTeDqjiR4Cbvtnl 9wvNglWQRH9RC1/U/XqaAaCVnaKNCY8qWRADEuSMqB1MsepO2SU77stq/BYOyhkq0K/hhH 5bB1Y8W0FIFJlVBSmnM54/3PKEGb0cmyBonw3WTYchFmBHl1qwwg2mWqiAkkAscmijjZp1 3eCvE3pS5NYL8aQCM2lhORLtnESXRprxsVBBAlGgV/fJ65NA14HQ4wvNiZHFSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791818935; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=j6ocoj/V6aJbXmR4Qm5OFIzA63NiP+fHWiuj303zuQA=; b=Fp54lAH8v+yXv0/u3G6HFCPa3TuNEGMPX0BwfoF5ag0baA5J+ua1Ufkk32Ic+sEYrJEG4G 3boBfu5kx9eK48o+b0sATYxJH7CB+A3bpl+wmCTB0LFmL248iUbpppxr6cMsC0zwtizv+2 yTVq4Mx9PKZmW/jAH8YIsnIwbzABuCYAd7Tpt85wHWlkoTFg+gPcqPJZwaUPJettQvIelq 1W3vtYC16MnqzDXczXed5ZAB0k8MI7BCmZfXUs9JtOrYe+Sz5XCFjiKlOWtNGsT5ub/NV0 hYWXNaqwAXtS0tzoGAEukVfGNlrB6122J/ZKRZRogmBT0djwZ6rPgv4/USkUqg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4j3LwR55B1zbNq for ; Mon, 12 Oct 2026 15:28:55 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 1c5fd by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Mon, 12 Oct 2026 15:28:55 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Cc: Kevin Bowling From: Ed Maste Subject: git: 5c2e2eba99f6 - stable/15 - aq: Invalidate the descriptor cache after stopping all rings List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches X-BeenThere: dev-commits-src-branches@freebsd.org Sender: owner-dev-commits-src-branches@FreeBSD.org List-Id: Commits to the stable branches of the FreeBSD src repository List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: emaste X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: 5c2e2eba99f633298e13b3cd53af5d63501a7d00 Auto-Submitted: auto-generated Date: Mon, 12 Oct 2026 15:28:55 +0000 Message-Id: <6accfcb7.1c5fd.53de3dee@gitrepo.freebsd.org> The branch stable/15 has been updated by emaste: URL: https://cgit.FreeBSD.org/src/commit/?id=5c2e2eba99f633298e13b3cd53af5d63501a7d00 commit 5c2e2eba99f633298e13b3cd53af5d63501a7d00 Author: Kevin Bowling AuthorDate: 2026-09-17 02:35:58 +0000 Commit: Ed Maste CommitDate: 2026-10-12 15:27:45 +0000 aq: Invalidate the descriptor cache after stopping all rings Atlantic controllers can retain receive descriptors and their data addresses after their rings are disabled. Reusing or releasing those mappings without invalidating the device cache has caused observed IOMMU and SMMU faults in the referenced Linux reports (7a1bb49461b1, ed4d81c4b3f2 and 7526183cfdbe). Move global cache invalidation out of the per-ring stop routine. Disable every ring first, toggle invalidation once, and wait for its completion indication. Exclude Atlantic A0, as in the upstream workaround. Report a completion timeout rather than silently discarding it. Reviewed by: nprice MFC after: 2 weeks Sponsored by: BBOX.io Differential Revision: https://reviews.freebsd.org/D59852 (cherry picked from commit 4993c1052f899b9a971815df5661ca241641ad8e) --- sys/dev/aq/aq_hw.c | 25 +++++++++++++++++++++++++ sys/dev/aq/aq_hw.h | 2 ++ sys/dev/aq/aq_hw_llh.c | 9 +++++++++ sys/dev/aq/aq_hw_llh.h | 3 +++ sys/dev/aq/aq_hw_llh_internal.h | 5 +++++ sys/dev/aq/aq_main.c | 4 ++++ sys/dev/aq/aq_ring.c | 4 ---- 7 files changed, 48 insertions(+), 4 deletions(-) diff --git a/sys/dev/aq/aq_hw.c b/sys/dev/aq/aq_hw.c index 934543937a57..5c926f2ed960 100644 --- a/sys/dev/aq/aq_hw.c +++ b/sys/dev/aq/aq_hw.c @@ -58,6 +58,31 @@ aq_hw_err_from_flags(struct aq_hw *hw) return (0); } +int +aq_hw_invalidate_descriptor_cache(struct aq_hw *hw) +{ + int error; + + /* Atlantic A0 does not implement this stop workaround. */ + if (IS_CHIP_FEATURE(hw, REVISION_A0)) + return (0); + + /* + * Cached Rx descriptors retain both descriptor and data addresses. + * Toggle the global cache invalidation only after every ring is down. + */ + rdm_rx_dma_desc_cache_init_tgl(hw); + error = aq_hw_err_from_flags(hw); + if (error != 0) + return (error); + + error = AQ_HW_WAIT_FOR(rdm_rx_dma_desc_cache_init_done_get(hw) != 0, + 1000, 10); + if (error != 0) + return (error); + return (aq_hw_err_from_flags(hw)); +} + inline uint32_t aq_hw_read_reg(struct aq_hw *hw, uint32_t reg) { diff --git a/sys/dev/aq/aq_hw.h b/sys/dev/aq/aq_hw.h index bf4925d139f9..67a2ee975888 100644 --- a/sys/dev/aq/aq_hw.h +++ b/sys/dev/aq/aq_hw.h @@ -408,6 +408,8 @@ int aq_hw_set_power(struct aq_hw *hw, unsigned int power_state); int aq_hw_err_from_flags(struct aq_hw *hw); +int aq_hw_invalidate_descriptor_cache(struct aq_hw *hw); + int hw_atl_b0_hw_vlan_promisc_set(struct aq_hw *hw, bool promisc); int hw_atl_b0_hw_vlan_set(struct aq_hw *hw, diff --git a/sys/dev/aq/aq_hw_llh.c b/sys/dev/aq/aq_hw_llh.c index 2369418a3681..d82413a946ea 100644 --- a/sys/dev/aq/aq_hw_llh.c +++ b/sys/dev/aq/aq_hw_llh.c @@ -1728,6 +1728,15 @@ rdm_rx_dma_desc_cache_init_tgl(struct aq_hw *aq_hw) ); } +uint32_t +rdm_rx_dma_desc_cache_init_done_get(struct aq_hw *aq_hw) +{ + return (AQ_READ_REG_BIT(aq_hw, + rdm_rx_dma_desc_cache_init_done_adr, + rdm_rx_dma_desc_cache_init_done_msk, + rdm_rx_dma_desc_cache_init_done_shift)); +} + void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw *aq_hw, uint32_t tx_pkt_buff_size_per_tc, uint32_t buffer) diff --git a/sys/dev/aq/aq_hw_llh.h b/sys/dev/aq/aq_hw_llh.h index 47011295aa4c..641e53b6da06 100644 --- a/sys/dev/aq/aq_hw_llh.h +++ b/sys/dev/aq/aq_hw_llh.h @@ -934,6 +934,9 @@ void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw *aq_hw, /* toggle rdm rx dma descriptor cache init */ void rdm_rx_dma_desc_cache_init_tgl(struct aq_hw *aq_hw); +/* get rdm rx dma descriptor cache init done */ +uint32_t rdm_rx_dma_desc_cache_init_done_get(struct aq_hw *aq_hw); + /* set tx path pad insert enable */ void tpb_tx_path_scp_ins_en_set(struct aq_hw *aq_hw, uint32_t tx_path_scp_ins_en); diff --git a/sys/dev/aq/aq_hw_llh_internal.h b/sys/dev/aq/aq_hw_llh_internal.h index fa1c9a83985b..48f3774216d2 100644 --- a/sys/dev/aq/aq_hw_llh_internal.h +++ b/sys/dev/aq/aq_hw_llh_internal.h @@ -395,6 +395,11 @@ /* default value of bitfield rdm_desc_init_i */ #define rdm_rx_dma_desc_cache_init_defaulT 0x0 +/* rdm_desc_init_done_i bitfield definitions */ +#define rdm_rx_dma_desc_cache_init_done_adr 0x00005a10 +#define rdm_rx_dma_desc_cache_init_done_msk 0x00000001 +#define rdm_rx_dma_desc_cache_init_done_shift 0 + /* rx int_desc_wrb_en bitfield definitions * preprocessor definitions for the bitfield "int_desc_wrb_en". * port="pif_rdm_int_desc_wrb_en_i" diff --git a/sys/dev/aq/aq_main.c b/sys/dev/aq/aq_main.c index e0d0d1727a95..edca88f34bba 100644 --- a/sys/dev/aq/aq_main.c +++ b/sys/dev/aq/aq_main.c @@ -886,6 +886,10 @@ aq_if_stop(if_ctx_t ctx) "could not stop RX ring %d\n", i); } + if (aq_hw_invalidate_descriptor_cache(hw) != 0) + device_printf(softc->dev, + "could not invalidate the RX descriptor cache\n"); + if (aq_hw_reset(&softc->hw, true) != 0) device_printf(softc->dev, "could not reset the MAC on stop\n"); memset(&softc->last_stats, 0, sizeof(softc->last_stats)); diff --git a/sys/dev/aq/aq_ring.c b/sys/dev/aq/aq_ring.c index e713c5089302..41b9a3912c4e 100644 --- a/sys/dev/aq/aq_ring.c +++ b/sys/dev/aq/aq_ring.c @@ -211,10 +211,6 @@ aq_ring_rx_stop(struct aq_hw *hw, struct aq_ring *ring) AQ_DBG_ENTERA("[%d]", ring->index); rdm_rx_desc_en_set(hw, 0U, ring->index); - /* Invalidate Descriptor Cache to prevent writing to the cached - * descriptors and to the data pointer of those descriptors - */ - rdm_rx_dma_desc_cache_init_tgl(hw); err = aq_hw_err_from_flags(hw); AQ_DBG_EXIT(err); return (err);