From nobody Tue Oct 06 07:51:34 2026 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4hzT3W256Rz6cWJd for ; Tue, 06 Oct 2026 07:51:35 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4hzT3V60qXz4H9Y for ; Tue, 06 Oct 2026 07:51:34 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791273094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=932dkggmn3uZpbZ7ard5Y0JwPPOccf8zQ66o2qxbuKc=; b=auie2Fxl0VT9aGgzJKoudAstpOwg7/KecpuC1eUlvd7mhiGdIHc0OsQXO5j0EawxpNISpb PPSdczvyWfWyBRnSARHy2oHcgVC0vV/nsjrkaKNMEoxsZzcjZGsgskgpItsxqBENAtCHAE SEALF0TYBbKCqH0I/PmUZBKP+YqqKgfiUs8Xc/GPvUERzzOVb3YX4Jfta1lMKNmqoY5Dlm 0EtMVnWiMbjuNBiVfXQG/HfcH79RATsj5HL/oQs/n/uXJDAneZdiLmN3FF5kUVCEsUIGSF ds3UyQ88R/OxTWJCqgeC8XyC95sODqKDxFVTiQihHPlKP7aB/5YVhBp/F45ylA== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1791273094; b=a+EEIb5pCEnuAG17qt0C58ngGdFxw36yYUBSQrb6AheNBsKLgpixwco8jHURpa/UxzPctj m3P2GUxcKdRlkBCigpkJAIsFHdS9Dx6lplCECMFUA6RKFAl547pEvfh6hotnoQ+kxhM/hP ngy9xogqCwiBhh6u6mv9NwU9qhIfaUuM42TnnF8BRrkOrHfOI7+0bvsTbiM4Cq/kgY9O3l vrwhkabZPkQ5K+kI9B+MRXqixBLY3bTJdv7rgoQjuXXQGON+YRcAzahDaZUjqABU8SjN82 Z26QlJk8EBMBsrtBk+PN8capwCgZthv4x5ZXoZGR5fPaovDZuuMDiU83/lgJ1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791273094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=932dkggmn3uZpbZ7ard5Y0JwPPOccf8zQ66o2qxbuKc=; b=Qb3yio1R12Q/XDBHbeafOM9hbHdcvG1vr9w3ZBqZMae+ipSHfpWVfy6l29XVqSk4wKprzV JpI3g8dq4IuvU/nckSq7l4dzT8f2oHfVUPts4aAKKj41dyVNhqfSQ5wmHguMTAL05thiRN zsSueNjpzRB8YFRe1LHy1qVI9Ih73mLL1c25Qrtw19siiDaeKshX9EhdhNVJbNoOHN0IZl SnT0/FmWCbx6tJHa4iabDF91cAmMcqW9t7Ez8U68dVai7nthIyqUZ8FMjm2GS6mTkJedjB wihVaXVqsrODKLjLEzCGjJYOq0OYxOQDtjLy1AmOvlWx1m9UnZH7ZwRIDZdpKQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4hzT3V3vyWzxcj for ; Tue, 06 Oct 2026 07:51:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 47b66 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Tue, 06 Oct 2026 07:51:34 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Jaeyoon Choi Subject: git: 1aaad60ae89a - stable/15 - ufshci: set HS series per platform and adapt type per gear List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-branches@freebsd.org Sender: owner-dev-commits-src-branches@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jaeyoon X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: 1aaad60ae89a132bbca0b1f1af85a5eb0f65f7b1 Auto-Submitted: auto-generated Date: Tue, 06 Oct 2026 07:51:34 +0000 Message-Id: <6ac4a886.47b66.35fc3845@gitrepo.freebsd.org> The branch stable/15 has been updated by jaeyoon: URL: https://cgit.FreeBSD.org/src/commit/?id=1aaad60ae89a132bbca0b1f1af85a5eb0f65f7b1 commit 1aaad60ae89a132bbca0b1f1af85a5eb0f65f7b1 Author: Jaeyoon Choi AuthorDate: 2026-09-02 01:50:09 +0000 Commit: Jaeyoon Choi CommitDate: 2026-10-06 06:28:07 +0000 ufshci: set HS series per platform and adapt type per gear The driver always asked for Rate-B. It never set the adaptation type. The Snapdragon X Elite firmware tunes the PHY for Rate-A. A Rate-B link dies at every gear there. HS-G4 and above need initial adaptation. This is a UniPro rule. It applies to every host. Add an hs_series field to the device tables. Use Rate-A on the Snapdragon X Elite. Keep Rate-B on the PCI hosts. A table entry without an HS series fails to attach. Set PA_TxHsAdaptType to initial adaptation at HS-G4 and above. Leave it alone below that. Hosts before UniPro 1.8 do not have it. The Galaxy Book 4 Edge now links at HS-G5 Rate-A. fio results (128k sequential, 4k random, posixaio): QD | SEQ_R(MiB/s) | SEQ_W(MiB/s) | RND_R(kIOPS) | RND_W(kIOPS) ----+--------------+--------------+--------------+------------- 1 | 1357 | 1221 | 12.1 | 27.2 4 | 3103 | 3234 | 46.5 | 92.9 32 | 3508 | 3238 | 176.4 | 125.0 Sequential writes land in the WriteBooster buffer. Sustained writes drop to 556 MiB/s once the buffer runs out. Reviewed by: imp (mentor) Sponsored by: Samsung Electronics Differential Revision: https://reviews.freebsd.org/D59298 (cherry picked from commit c09daa33d6ffbbd1956bfe4dcd9ca746192d6940) --- sys/dev/ufshci/ufshci.h | 4 ++++ sys/dev/ufshci/ufshci_acpi.c | 9 +++++++-- sys/dev/ufshci/ufshci_ctrlr.c | 7 +++++++ sys/dev/ufshci/ufshci_dev.c | 11 +++++++---- sys/dev/ufshci/ufshci_pci.c | 10 +++++++--- sys/dev/ufshci/ufshci_private.h | 1 + 6 files changed, 33 insertions(+), 9 deletions(-) diff --git a/sys/dev/ufshci/ufshci.h b/sys/dev/ufshci/ufshci.h index c2bef5c9a807..ab55c0af938f 100644 --- a/sys/dev/ufshci/ufshci.h +++ b/sys/dev/ufshci/ufshci.h @@ -41,6 +41,8 @@ #define PA_TxTermination 0x1569 #define PA_RxTermination 0x1584 #define PA_HSSeries 0x156A +#define UFSHCI_HS_SERIES_A 1 +#define UFSHCI_HS_SERIES_B 2 #define PA_PWRModeUserData0 0x15B0 #define PA_PWRModeUserData1 0x15B1 #define PA_PWRModeUserData2 0x15B2 @@ -49,6 +51,8 @@ #define PA_PWRModeUserData5 0x15B5 #define PA_TxHsAdaptType 0x15D4 +#define PA_INITIAL_ADAPT 1 +#define PA_NO_ADAPT 3 #define PA_PWRMode 0x1571 #define DME_LocalFC0ProtectionTimeOutVal 0xD041 diff --git a/sys/dev/ufshci/ufshci_acpi.c b/sys/dev/ufshci/ufshci_acpi.c index f96a4c29e15e..00078a47dec3 100644 --- a/sys/dev/ufshci/ufshci_acpi.c +++ b/sys/dev/ufshci/ufshci_acpi.c @@ -49,17 +49,21 @@ static struct ufshci_acpi_device { const char *hid; const char *desc; uint32_t ref_clk; + uint32_t hs_series; uint32_t quirks; } ufshci_acpi_devices[] = { /* * The SoC feeds the device 38.4 MHz from its CXO. The firmware * has no property for it. Verified on the Galaxy Book 4 Edge. + * + * The firmware calibrates the PHY for Rate-A. A Rate-B link + * comes up dead at every gear. */ { "QCOM24A5", "Qualcomm Snapdragon X Elite UFS Host Controller", - UFSHCI_REF_CLK_38_4MHz, + UFSHCI_REF_CLK_38_4MHz, UFSHCI_HS_SERIES_A, UFSHCI_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH | UFSHCI_QUIRK_BROKEN_LSDBS_MCQS_CAP }, - { 0x00000000, NULL, 0, 0 } + { 0x00000000, NULL, 0, 0, 0 } }; static char *ufshci_acpi_ids[] = { "QCOM24A5", NULL }; @@ -97,6 +101,7 @@ ufshci_acpi_probe(device_t dev) if (acpi_dev->hid) { ctrlr->quirks = acpi_dev->quirks; ctrlr->ref_clk = acpi_dev->ref_clk; + ctrlr->hs_series = acpi_dev->hs_series; } if (acpi_dev->desc) { diff --git a/sys/dev/ufshci/ufshci_ctrlr.c b/sys/dev/ufshci/ufshci_ctrlr.c index 69b6869e98e2..b3b9abbe867c 100644 --- a/sys/dev/ufshci/ufshci_ctrlr.c +++ b/sys/dev/ufshci/ufshci_ctrlr.c @@ -375,6 +375,13 @@ ufshci_ctrlr_construct(struct ufshci_controller *ctrlr, device_t dev) if (!(ctrlr->is_single_db_supported || ctrlr->is_mcq_supported)) return (ENXIO); + /* Every device table entry must name the HS series. */ + if (ctrlr->hs_series == 0) { + ufshci_printf(ctrlr, + "hs_series is missing from the device table\n"); + return (ENXIO); + } + /* * The maximum transfer size supported by UFSHCI spec is 65535 * 256 KiB * However, we limit the maximum transfer size to 1MiB(256 * 4KiB) for diff --git a/sys/dev/ufshci/ufshci_dev.c b/sys/dev/ufshci/ufshci_dev.c index dd467f85c795..28c91828a925 100644 --- a/sys/dev/ufshci/ufshci_dev.c +++ b/sys/dev/ufshci/ufshci_dev.c @@ -320,8 +320,6 @@ ufshci_dev_init_unipro(struct ufshci_controller *ctrlr) int ufshci_dev_init_uic_power_mode(struct ufshci_controller *ctrlr) { - /* HSSerise: A = 1, B = 2 */ - const uint32_t hs_series = 2; /* * TX/RX PWRMode: * - TX[3:0], RX[7:4] @@ -386,8 +384,13 @@ ufshci_dev_init_uic_power_mode(struct ufshci_controller *ctrlr) if (ufshci_uic_send_dme_set(ctrlr, PA_RxTermination, true)) return (ENXIO); - /* Set HSSerise (A = 1, B = 2) */ - if (ufshci_uic_send_dme_set(ctrlr, PA_HSSeries, hs_series)) + /* Set HSSeries */ + if (ufshci_uic_send_dme_set(ctrlr, PA_HSSeries, ctrlr->hs_series)) + return (ENXIO); + + /* HS-G4 and above need initial adaptation. */ + if (ctrlr->hs_gear >= 4 && + ufshci_uic_send_dme_set(ctrlr, PA_TxHsAdaptType, PA_INITIAL_ADAPT)) return (ENXIO); /* Set Timeout values */ diff --git a/sys/dev/ufshci/ufshci_pci.c b/sys/dev/ufshci/ufshci_pci.c index b6b8124bc3a6..3cc184bef714 100644 --- a/sys/dev/ufshci/ufshci_pci.c +++ b/sys/dev/ufshci/ufshci_pci.c @@ -49,20 +49,23 @@ static struct _pcsid { uint32_t devid; const char *desc; uint32_t ref_clk; + uint32_t hs_series; uint32_t quirks; } pci_ids[] = { { 0x131b36, "QEMU UFS Host Controller", UFSHCI_REF_CLK_19_2MHz, + UFSHCI_HS_SERIES_B, UFSHCI_QUIRK_IGNORE_UIC_POWER_MODE | UFSHCI_QUIRK_NOT_SUPPORT_ABORT_TASK | UFSHCI_QUIRK_SKIP_WELL_KNOWN_LUNS }, { 0x98fa8086, "Intel Lakefield UFS Host Controller", - UFSHCI_REF_CLK_19_2MHz, + UFSHCI_REF_CLK_19_2MHz, UFSHCI_HS_SERIES_B, UFSHCI_QUIRK_LONG_PEER_PA_TACTIVATE | UFSHCI_QUIRK_WAIT_AFTER_POWER_MODE_CHANGE | UFSHCI_QUIRK_CHANGE_LANE_AND_GEAR_SEPARATELY | UFSHCI_QUIRK_BROKEN_AUTO_HIBERNATE }, { 0x54ff8086, "Intel Alder Lake-N UFS Host Controller", - UFSHCI_REF_CLK_19_2MHz, UFSHCI_QUIRK_BROKEN_AUTO_HIBERNATE }, - { 0x00000000, NULL } }; + UFSHCI_REF_CLK_19_2MHz, UFSHCI_HS_SERIES_B, + UFSHCI_QUIRK_BROKEN_AUTO_HIBERNATE }, + { 0x00000000, NULL, 0, 0, 0 } }; static int ufshci_pci_probe(device_t device) @@ -77,6 +80,7 @@ ufshci_pci_probe(device_t device) if (ep->devid) { ctrlr->quirks = ep->quirks; ctrlr->ref_clk = ep->ref_clk; + ctrlr->hs_series = ep->hs_series; } if (ep->desc) { diff --git a/sys/dev/ufshci/ufshci_private.h b/sys/dev/ufshci/ufshci_private.h index 7b74faf95c53..221abb9a9892 100644 --- a/sys/dev/ufshci/ufshci_private.h +++ b/sys/dev/ufshci/ufshci_private.h @@ -340,6 +340,7 @@ struct ufshci_controller { 256 /* Some controllers have their LSDB and MCQS fields reset to 0. */ uint32_t ref_clk; + uint32_t hs_series; struct cam_sim *ufshci_sim; struct cam_path *ufshci_path;