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Sun, 9 Nov 2025 00:38:20 GMT (envelope-from git) Date: Sun, 9 Nov 2025 00:38:20 GMT Message-Id: <202511090038.5A90cKBd097706@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Konstantin Belousov Subject: git: fe5f45696edd - stable/14 - atomic.9: provide fine details about CAS memory model MD semantic List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-branches@freebsd.org Sender: owner-dev-commits-src-branches@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: kib X-Git-Repository: src X-Git-Refname: refs/heads/stable/14 X-Git-Reftype: branch X-Git-Commit: fe5f45696edd6e00657b339e8f2cf554a5f8ede1 Auto-Submitted: auto-generated The branch stable/14 has been updated by kib: URL: https://cgit.FreeBSD.org/src/commit/?id=fe5f45696edd6e00657b339e8f2cf554a5f8ede1 commit fe5f45696edd6e00657b339e8f2cf554a5f8ede1 Author: Konstantin Belousov AuthorDate: 2025-09-26 06:58:36 +0000 Commit: Konstantin Belousov CommitDate: 2025-11-09 00:37:06 +0000 atomic.9: provide fine details about CAS memory model MD semantic (cherry picked from commit 269b1c238806c7fb8835a0510b224c466ca3efa0) --- share/man/man9/atomic.9 | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/share/man/man9/atomic.9 b/share/man/man9/atomic.9 index 19ab7e0fbdbd..af94b5773f0e 100644 --- a/share/man/man9/atomic.9 +++ b/share/man/man9/atomic.9 @@ -242,6 +242,33 @@ section. However, they will not prevent the compiler or processor from moving loads or stores into the critical section, which does not violate the semantics of a mutex. +.Ss Architecture-dependent caveats for compare-and-swap +The +.Fn atomic_[f]cmpset_ +operations, specifically those without explicitly specified memory +ordering, are defined as relaxed. +Consequently, a thread's accesses to memory locations different from +that of the atomic operation can be reordered in relation to the +atomic operation. +.Pp +However, the implementation on the +.Sy amd64 +and +.Sy i386 +architectures provide sequentially consistent semantics. +In particular, the reordering mentioned above cannot occur. +.Pp +On the +.Sy arm64/aarch64 +architecture, the operation may include either acquire +semantics on the constituent load or release semantics +on the constituent store. +This means that accesses to other locations in program order +before the atomic, might be observed as executed after the load +that is the part of the atomic operation (but not after the store +from the operation due to release). +Similarly, accesses after the atomic might be observed as executed +before the store. .Ss Thread Fence Operations Alternatively, a programmer can use atomic thread fence operations to constrain the reordering of accesses.