git: 711422d54795 - releng/14.0 - Merge commit f800c1f3b207 from llvm-project (by Arthur Eubanks):

The branch releng/14.0 has been updated by gordon:

URL: https://cgit.FreeBSD.org/src/commit/?id=711422d54795fb4fbef16fd1f1afcee6ed4510f4

commit 711422d54795fb4fbef16fd1f1afcee6ed4510f4
Author:     Dimitry Andric <dim@FreeBSD.org>
AuthorDate: 2024-03-04 20:30:54 +0000
Commit:     Gordon Tetlow <gordon@FreeBSD.org>
CommitDate: 2024-03-28 03:13:14 +0000

    Merge commit f800c1f3b207 from llvm-project (by Arthur Eubanks):
    
      [PEI] Don't zero out noreg operands
    
      A tail call may have $noreg operands.
    
      Fixes a crash.
    
      Reviewed By: xgupta
    
      Differential Revision: https://reviews.llvm.org/D156485
    
    This should fix an assertion failure building qemu, specifically those
    parts using -fzero-call-used-regs.
    
    Reported by:    Daniel Berrangé <dan-freebsd@berrange.com>
    PR:             277474
    MFC after:      3 days
    Approved by:    so
    Security:       FreeBSD-EN-24:07.clang
    
    (cherry picked from commit a39b3aa463f3474fabb3aedb5aecf943b54b4357)
    (cherry picked from commit fc31d474c40a50066310b3d03a8eb0724a00609d)
---
 contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index cc70ec477650..f4e7b57e9284 100644
--- a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1289,6 +1289,8 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
           continue;
 
         MCRegister Reg = MO.getReg();
+        if (!Reg)
+          continue;
 
         // This picks up sibling registers (e.q. %al -> %ah).
         for (MCRegUnitIterator Unit(Reg, &TRI); Unit.isValid(); ++Unit)
@@ -1312,8 +1314,11 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
         if (!MO.isReg())
           continue;
 
-        for (const MCPhysReg &Reg :
-             TRI.sub_and_superregs_inclusive(MO.getReg()))
+        MCRegister Reg = MO.getReg();
+        if (!Reg)
+          continue;
+
+        for (const MCPhysReg Reg : TRI.sub_and_superregs_inclusive(Reg))
           RegsToZero.reset(Reg);
       }
     }