git: 78c98588c950 - stable/14 - nvme: Add some bits from NVMe 2.0c spec.

The branch stable/14 has been updated by mav:

URL: https://cgit.FreeBSD.org/src/commit/?id=78c98588c9507e708deba5fe58ae550e01759824

commit 78c98588c9507e708deba5fe58ae550e01759824
Author:     Alexander Motin <mav@FreeBSD.org>
AuthorDate: 2023-12-27 18:50:54 +0000
Commit:     Alexander Motin <mav@FreeBSD.org>
CommitDate: 2024-01-03 01:40:31 +0000

    nvme: Add some bits from NVMe 2.0c spec.
    
    MFC after:      1 week
    
    (cherry picked from commit b46c7b1ed4e5307c689df72ea8a0b69e02456905)
---
 sys/dev/nvme/nvme.h       | 26 +++++++++++++++++++++++++-
 sys/dev/nvme/nvme_ctrlr.c |  8 ++++++--
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/sys/dev/nvme/nvme.h b/sys/dev/nvme/nvme.h
index e9b1b32c3777..3e39803f68ab 100644
--- a/sys/dev/nvme/nvme.h
+++ b/sys/dev/nvme/nvme.h
@@ -91,6 +91,8 @@
 #define NVME_CAP_HI_REG_CSS_NVM_MASK			(0x1)
 #define NVME_CAP_HI_REG_BPS_SHIFT			(13)
 #define NVME_CAP_HI_REG_BPS_MASK			(0x1)
+#define NVME_CAP_HI_REG_CPS_SHIFT			(14)
+#define NVME_CAP_HI_REG_CPS_MASK			(0x3)
 #define NVME_CAP_HI_REG_MPSMIN_SHIFT			(16)
 #define NVME_CAP_HI_REG_MPSMIN_MASK			(0xF)
 #define NVME_CAP_HI_REG_MPSMAX_SHIFT			(20)
@@ -99,6 +101,12 @@
 #define NVME_CAP_HI_REG_PMRS_MASK			(0x1)
 #define NVME_CAP_HI_REG_CMBS_SHIFT			(25)
 #define NVME_CAP_HI_REG_CMBS_MASK			(0x1)
+#define NVME_CAP_HI_REG_NSSS_SHIFT			(26)
+#define NVME_CAP_HI_REG_NSSS_MASK			(0x1)
+#define NVME_CAP_HI_REG_CRWMS_SHIFT			(27)
+#define NVME_CAP_HI_REG_CRWMS_MASK			(0x1)
+#define NVME_CAP_HI_REG_CRIMS_SHIFT			(28)
+#define NVME_CAP_HI_REG_CRIMS_MASK			(0x1)
 #define NVME_CAP_HI_DSTRD(x) \
 	(((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
 #define NVME_CAP_HI_NSSRS(x) \
@@ -109,6 +117,8 @@
 	(((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
 #define NVME_CAP_HI_BPS(x) \
 	(((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK)
+#define NVME_CAP_HI_CPS(x) \
+	(((x) >> NVME_CAP_HI_REG_CPS_SHIFT) & NVME_CAP_HI_REG_CPS_MASK)
 #define NVME_CAP_HI_MPSMIN(x) \
 	(((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
 #define NVME_CAP_HI_MPSMAX(x) \
@@ -117,6 +127,12 @@
 	(((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK)
 #define NVME_CAP_HI_CMBS(x) \
 	(((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK)
+#define NVME_CAP_HI_NSSS(x) \
+	(((x) >> NVME_CAP_HI_REG_NSSS_SHIFT) & NVME_CAP_HI_REG_NSSS_MASK)
+#define NVME_CAP_HI_CRWMS(x) \
+	(((x) >> NVME_CAP_HI_REG_CRWMS_SHIFT) & NVME_CAP_HI_REG_CRWMS_MASK)
+#define NVME_CAP_HI_CRIMS(x) \
+	(((x) >> NVME_CAP_HI_REG_CRIMS_SHIFT) & NVME_CAP_HI_REG_CRIMS_MASK)
 
 #define NVME_CC_REG_EN_SHIFT				(0)
 #define NVME_CC_REG_EN_MASK				(0x1)
@@ -132,6 +148,8 @@
 #define NVME_CC_REG_IOSQES_MASK				(0xF)
 #define NVME_CC_REG_IOCQES_SHIFT			(20)
 #define NVME_CC_REG_IOCQES_MASK				(0xF)
+#define NVME_CC_REG_CRIME_SHIFT				(24)
+#define NVME_CC_REG_CRIME_MASK				(0x1)
 
 #define NVME_CSTS_REG_RDY_SHIFT				(0)
 #define NVME_CSTS_REG_RDY_MASK				(0x1)
@@ -143,6 +161,8 @@
 #define NVME_CSTS_REG_NVSRO_MASK			(0x1)
 #define NVME_CSTS_REG_PP_SHIFT				(5)
 #define NVME_CSTS_REG_PP_MASK				(0x1)
+#define NVME_CSTS_REG_ST_SHIFT				(6)
+#define NVME_CSTS_REG_ST_MASK				(0x1)
 
 #define NVME_CSTS_GET_SHST(csts)			(((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK)
 
@@ -616,7 +636,11 @@ struct nvme_registers {
 	uint64_t	bpmbl;	/* Boot Partition Memory Buffer Location */
 	uint64_t	cmbmsc;	/* Controller Memory Buffer Memory Space Control */
 	uint32_t	cmbsts;	/* Controller Memory Buffer Status */
-	uint8_t		reserved3[3492]; /* 5Ch - DFFh */
+	uint32_t	cmbebs;	/* Controller Memory Buffer Elasticity Buffer Size */
+	uint32_t	cmbswtp;/* Controller Memory Buffer Sustained Write Throughput */
+	uint32_t	nssd;	/* NVM Subsystem Shutdown */
+	uint32_t	crto;	/* Controller Ready Timeouts */
+	uint8_t		reserved3[3476]; /* 6Ch - DFFh */
 	uint32_t	pmrcap;	/* Persistent Memory Capabilities */
 	uint32_t	pmrctl;	/* Persistent Memory Region Control */
 	uint32_t	pmrsts;	/* Persistent Memory Region Status */
diff --git a/sys/dev/nvme/nvme_ctrlr.c b/sys/dev/nvme/nvme_ctrlr.c
index 5a57bbbd53af..55573669562c 100644
--- a/sys/dev/nvme/nvme_ctrlr.c
+++ b/sys/dev/nvme/nvme_ctrlr.c
@@ -1416,15 +1416,19 @@ nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev)
 	ctrlr->cap_hi = cap_hi = nvme_mmio_read_4(ctrlr, cap_hi);
 	if (bootverbose) {
 		device_printf(dev, "CapHi: 0x%08x: DSTRD %u%s, CSS %x%s, "
-		    "MPSMIN %u, MPSMAX %u%s%s\n", cap_hi,
+		    "CPS %x, MPSMIN %u, MPSMAX %u%s%s%s%s%s\n", cap_hi,
 		    NVME_CAP_HI_DSTRD(cap_hi),
 		    NVME_CAP_HI_NSSRS(cap_hi) ? ", NSSRS" : "",
 		    NVME_CAP_HI_CSS(cap_hi),
 		    NVME_CAP_HI_BPS(cap_hi) ? ", BPS" : "",
+		    NVME_CAP_HI_CPS(cap_hi),
 		    NVME_CAP_HI_MPSMIN(cap_hi),
 		    NVME_CAP_HI_MPSMAX(cap_hi),
 		    NVME_CAP_HI_PMRS(cap_hi) ? ", PMRS" : "",
-		    NVME_CAP_HI_CMBS(cap_hi) ? ", CMBS" : "");
+		    NVME_CAP_HI_CMBS(cap_hi) ? ", CMBS" : "",
+		    NVME_CAP_HI_NSSS(cap_hi) ? ", NSSS" : "",
+		    NVME_CAP_HI_CRWMS(cap_hi) ? ", CRWMS" : "",
+		    NVME_CAP_HI_CRIMS(cap_hi) ? ", CRIMS" : "");
 	}
 	if (bootverbose) {
 		vs = nvme_mmio_read_4(ctrlr, vs);