From nobody Mon Sep 25 11:01:06 2023 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RvKg706YFz4vNkQ; Mon, 25 Sep 2023 11:01:07 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RvKg64jlrz3N2S; Mon, 25 Sep 2023 11:01:06 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1695639666; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=mP8jJUGo8S7f5q0zEUBpbrY2bO8MB1wZTpV4Sxs9yNI=; b=Vqy7OWfvL0IPsH7tHAsvEozjm9QESpgLfH7tIDU90obIZgqbGUtFFn63A51Jl4q6CJlquS lPxLsI73dUNaPIWFSKovsJVJDF87Iua7RTlnJI62uue00FhyzEJMFTsmdO1T+k32NWJKlH h/97BWJ0n/kIQgtpyjLkZ7luAs+jJJXm1ycbvXxHBKgVtLHmx7RiaRD+5Xgq4M/yhhLrmP ICdNkGV8cv/gwMlHOevy1CNaUxNtqh2XgrzEGVbVQS4L6gDvYo9Hu0eNtMHco8eIXqzgeb V8JkXSlkdyzW26EPX87cP3w+8utp+kxrxDSdO2vWlJewOoTUK3zbNLQB5kz0+Q== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1695639666; a=rsa-sha256; cv=none; b=aOwC3X1TQO3jejYS4wgtzhCEBKLJobkbqwTaYupRJY93GGm6e2OMmsmeCzZvgzSPD/hGet 945ophmpqo52VBs6hbIb8fepFTxRQdUJc65nKh52ISrrvtBPCMSjqvyiRf0p7Nfj5ooS9n VDs++DyoAIEdtYUpboUdKbNzOI3bpoAdUtreh1Kmli7eXKI/bYCuHa5chdbAsi4eVVzJKT 6MRH6win4Q20kKH+8SMWMFkRjgpuu+d/QPoO29QEHs7VgYOg9XJsoxOCT/EsNDydWPSXtr nlEhkarC061ksTKlA98loXQW3cmZSc5QD4HSnXaSL80+fgNGZdglSHggYLy6fA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1695639666; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=mP8jJUGo8S7f5q0zEUBpbrY2bO8MB1wZTpV4Sxs9yNI=; b=fe6ATJZvC/aJQ8rlIe+0P6wE4BUci8y5W6sTjYmaXDo/JMeOVc3Xloqf7HW/ujscUUTuVF L23lmcDcE4XBBmbekXGJXs37AHP9bh4fcmikpkg/joUo4wy1jnXp/o2jZ+p48EQ2QA09O9 cAW0k4ezO56MrKnMRl8EP3Lnp1KkKISngePlotMfsRQCkjGu8dh3iRR0783QSf7lbFg4Mb Kqc4og3eSJ9vNfz6gg2Hrmy8JIb7tngCB/7nc+8wiPzG+FIqElXKDACpDRVJWSFRiMAoNc fhoPBweQXpC5FGO4Hq63OIBHWblGcja/lIWkcU3ETmqMBbW5lFifceYq7UMGVQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4RvKg63plZz1QL7; Mon, 25 Sep 2023 11:01:06 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.17.1/8.17.1) with ESMTP id 38PB16iY053303; Mon, 25 Sep 2023 11:01:06 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.17.1/8.17.1/Submit) id 38PB16Vd053300; Mon, 25 Sep 2023 11:01:06 GMT (envelope-from git) Date: Mon, 25 Sep 2023 11:01:06 GMT Message-Id: <202309251101.38PB16Vd053300@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Andrew Turner Subject: git: 75fa285b8988 - stable/13 - arm64: Update the ID_AA64ISAR1_EL1 fields List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: 75fa285b8988a01ea3873c0986d9539c342f0b4b Auto-Submitted: auto-generated The branch stable/13 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=75fa285b8988a01ea3873c0986d9539c342f0b4b commit 75fa285b8988a01ea3873c0986d9539c342f0b4b Author: Andrew Turner AuthorDate: 2023-07-06 10:01:11 +0000 Commit: Andrew Turner CommitDate: 2023-09-25 08:41:33 +0000 arm64: Update the ID_AA64ISAR1_EL1 fields While here move to decimal for the _op and _CR definitions to be used by a future macro to define the register when the assembler doesn't know about it. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D40889 (cherry picked from commit de01309926e21e1cff196b6b23cff6c52064aa0e) --- sys/arm64/arm64/identcpu.c | 15 +++++++++++++++ sys/arm64/include/armreg.h | 23 ++++++++++++++++++----- 2 files changed, 33 insertions(+), 5 deletions(-) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 8851cd952b7b..663e465d4149 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -635,6 +635,18 @@ static const struct mrs_field id_aa64isar0_fields[] = { /* ID_AA64ISAR1_EL1 */ +static const struct mrs_field_value id_aa64isar1_ls64[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LS64, NONE, IMPL), + MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_V, "LS64v"), + MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_ACCDATA, "LS64+ACCDATA"), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64isar1_xs[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, XS, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field_value id_aa64isar1_i8mm[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL), MRS_FIELD_VALUE_END, @@ -657,6 +669,7 @@ static const struct mrs_field_hwcap id_aa64isar1_dgh_caps[] = { static const struct mrs_field_value id_aa64isar1_bf16[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL), + MRS_FIELD_VALUE(ID_AA64ISAR1_BF16_EBF, "EBF16"), MRS_FIELD_VALUE_END, }; @@ -770,6 +783,8 @@ static const struct mrs_field_hwcap id_aa64isar1_dpb_caps[] = { }; static const struct mrs_field id_aa64isar1_fields[] = { + MRS_FIELD(ID_AA64ISAR1, LS64, false, MRS_EXACT, id_aa64isar1_ls64), + MRS_FIELD(ID_AA64ISAR1, XS, false, MRS_EXACT, id_aa64isar1_xs), MRS_FIELD_HWCAP(ID_AA64ISAR1, I8MM, false, MRS_LOWER, id_aa64isar1_i8mm, id_aa64isar1_i8mm_caps), MRS_FIELD_HWCAP(ID_AA64ISAR1, DGH, false, MRS_LOWER, id_aa64isar1_dgh, diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 1c9ea3b630f4..63188f112f51 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -677,11 +677,11 @@ /* ID_AA64ISAR1_EL1 */ #define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1) -#define ID_AA64ISAR1_EL1_op0 0x3 -#define ID_AA64ISAR1_EL1_op1 0x0 -#define ID_AA64ISAR1_EL1_CRn 0x0 -#define ID_AA64ISAR1_EL1_CRm 0x6 -#define ID_AA64ISAR1_EL1_op2 0x1 +#define ID_AA64ISAR1_EL1_op0 3 +#define ID_AA64ISAR1_EL1_op1 0 +#define ID_AA64ISAR1_EL1_CRn 0 +#define ID_AA64ISAR1_EL1_CRm 6 +#define ID_AA64ISAR1_EL1_op2 1 #define ID_AA64ISAR1_DPB_SHIFT 0 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) @@ -752,6 +752,7 @@ #define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) #define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT) #define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT) +#define ID_AA64ISAR1_BF16_EBF (UL(0x2) << ID_AA64ISAR1_BF16_SHIFT) #define ID_AA64ISAR1_DGH_SHIFT 48 #define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT) #define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) @@ -762,6 +763,18 @@ #define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) #define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) #define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) +#define ID_AA64ISAR1_XS_SHIFT 56 +#define ID_AA64ISAR1_XS_MASK (UL(0xf) << ID_AA64ISAR1_XS_SHIFT) +#define ID_AA64ISAR1_XS_VAL(x) ((x) & ID_AA64ISAR1_XS_MASK) +#define ID_AA64ISAR1_XS_NONE (UL(0x0) << ID_AA64ISAR1_XS_SHIFT) +#define ID_AA64ISAR1_XS_IMPL (UL(0x1) << ID_AA64ISAR1_XS_SHIFT) +#define ID_AA64ISAR1_LS64_SHIFT 60 +#define ID_AA64ISAR1_LS64_MASK (UL(0xf) << ID_AA64ISAR1_LS64_SHIFT) +#define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK) +#define ID_AA64ISAR1_LS64_NONE (UL(0x0) << ID_AA64ISAR1_LS64_SHIFT) +#define ID_AA64ISAR1_LS64_IMPL (UL(0x1) << ID_AA64ISAR1_LS64_SHIFT) +#define ID_AA64ISAR1_LS64_V (UL(0x2) << ID_AA64ISAR1_LS64_SHIFT) +#define ID_AA64ISAR1_LS64_ACCDATA (UL(0x3) << ID_AA64ISAR1_LS64_SHIFT) /* ID_AA64ISAR2_EL1 */ #define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1)