git: 0fb5ae0c7c3d - stable/13 - Add more arm64 special register values

The branch stable/13 has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=0fb5ae0c7c3d8adf4d1e0d8badf7e724db279f8a

commit 0fb5ae0c7c3d8adf4d1e0d8badf7e724db279f8a
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2023-06-09 17:46:58 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2023-09-25 08:41:32 +0000

    Add more arm64 special register values
    
    These will be used to simplify the kernel special register handling.
    
    Sponsored by:   Arm Ltd
    
    (cherry picked from commit 178747a1586d48a8063014d7b8528ec47205e1bf)
---
 sys/arm64/include/armreg.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 9b60ea2a6263..d307781f2d01 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1247,6 +1247,14 @@
 #define	MDSCR_MDE_SHIFT			15
 #define	MDSCR_MDE			(UL(0x1) << MDSCR_MDE_SHIFT)
 
+/* MIDR_EL1 - Main ID Register */
+#define	MIDR_EL1			MRS_REG(MIDR_EL1)
+#define	MIDR_EL1_op0			3
+#define	MIDR_EL1_op1			0
+#define	MIDR_EL1_CRn			0
+#define	MIDR_EL1_CRm			0
+#define	MIDR_EL1_op2			0
+
 /* MPIDR_EL1 - Multiprocessor Affinity Register */
 #define	MPIDR_EL1			MRS_REG(MPIDR_EL1)
 #define	MPIDR_EL1_op0			3
@@ -1886,6 +1894,14 @@
 #define	PSR_SETTABLE_32	PSR_FLAGS
 #define	PSR_SETTABLE_64	(PSR_FLAGS | PSR_SS)
 
+/* REVIDR_EL1 - Revision ID Register */
+#define	REVIDR_EL1			MRS_REG(REVIDR_EL1)
+#define	REVIDR_EL1_op0			3
+#define	REVIDR_EL1_op1			0
+#define	REVIDR_EL1_CRn			0
+#define	REVIDR_EL1_CRm			0
+#define	REVIDR_EL1_op2			6
+
 /* TCR_EL1 - Translation Control Register */
 /* Bits 63:59 are reserved */
 #define	TCR_TCMA1_SHIFT		58