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Harmening" Subject: git: 95e02a419224 - stable/12 - Intel DMAR: remove parsing of 6-level paging capability List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jah X-Git-Repository: src X-Git-Refname: refs/heads/stable/12 X-Git-Reftype: branch X-Git-Commit: 95e02a41922437f0d616f9b61dfff5605ad7c601 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch stable/12 has been updated by jah: URL: https://cgit.FreeBSD.org/src/commit/?id=95e02a41922437f0d616f9b61dfff5605ad7c601 commit 95e02a41922437f0d616f9b61dfff5605ad7c601 Author: Jason A. Harmening AuthorDate: 2023-05-01 16:22:39 +0000 Commit: Jason A. Harmening CommitDate: 2023-05-06 01:00:34 +0000 Intel DMAR: remove parsing of 6-level paging capability Early versions of the VT-d spec mentioned 6-level paging support as a possible value for the SAGAW capability, but later versions removed it and SAGAW=0x10 is currently listed as a reserved value. The 6-level (agaw=64) entry in sagaw_bits is furthermore problematic with clang15 because the attempted comparison against 1ULL << 64 in dmar_maxaddr2mgaw() causes the compiler to elide the last iteration of the initial loop, which bypasses the subsequent logic to find the greatest HW-supported address width. This results in 5-level paging always being selected regardless of whether the hardware supports it, which can result address translation failure due to invalid context- entry programming. Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D39896 (cherry picked from commit 6f378116e9bf982b8246d033d81cb64d52b24462) --- sys/x86/iommu/intel_utils.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/sys/x86/iommu/intel_utils.c b/sys/x86/iommu/intel_utils.c index dd46c4290527..9e9c59d98fd0 100644 --- a/sys/x86/iommu/intel_utils.c +++ b/sys/x86/iommu/intel_utils.c @@ -100,9 +100,14 @@ static const struct sagaw_bits_tag { {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL, .pglvl = 4}, {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL, - .pglvl = 5}, - {.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL, - .pglvl = 6} + .pglvl = 5} + /* + * 6-level paging (DMAR_CAP_SAGAW_6LVL) is not supported on any + * current VT-d hardware and its SAGAW field value is listed as + * reserved in the VT-d spec. If support is added in the future, + * this structure and the logic in dmar_maxaddr2mgaw() will need + * to change to avoid attempted comparison against 1ULL << 64. + */ }; bool