From nobody Mon Jun 12 13:50:22 2023 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4QftNt4HgRz4cGcx; Mon, 12 Jun 2023 13:50:22 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4QftNt3Xzvz47fP; Mon, 12 Jun 2023 13:50:22 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1686577822; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=2aEYWYhEcX89Os3RwPwqb0lUXclFlW1nKmpId7hQfwY=; b=elGqYQZ/p5Obkdb9kOYsSs7n6RFHuPEk3ifsMZg4vCCBiwDYaWzpE6hLaieNDMcYvq2Cc7 IuqS+8DLW3+f/cVy+CmmNMJGy9CkquFi6Z7iuW1RMAnbMGyX4+wBdwWQ6njCpo/XeITIOh UR+CO4fz6eIdhoS+8sPV6vQzrDpylyGWy2ElRTrjWorw6nRqdeSmZSFabCBmBCu9XT+R7+ uYheQSnJ2h+3NTPhkbzDr0FJ3YeMUGNIDSho7fW28NczDy5OhKtT388UxbE9hqjWKJ073H ZQIGB39cG7V+7XQR7cD/fEZUKn/HghBnr83cdt8PgdLpIFKnXuZYFDcXfA0zyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1686577822; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=2aEYWYhEcX89Os3RwPwqb0lUXclFlW1nKmpId7hQfwY=; b=bnOSFtRWxEeEeN0l2HETxOQTgo4JUBE528XiwfgH8NKGRrVcD4IZWAaIPkf0addyakJ0kb AEUKwHvzuHpVpPs8rWayYPRTiwJKDDsb4SfVyHwatf/E3RF88e/kcJlgfzoA5GbTBLMX4f +jbVGpCSwyIdhDxiZMy2yl/FJSkxu3F2I7ij+ks9dGfltTvkU67zGS63ChtHTmh2tsv/8/ DSdFsHcQewKoWC8a56oCbMTcHmnktc9UytkHEo4JitodWpbccnfFv6hAbkLIIvDgvatHQz 2CGFW/HEN9m8zvgWFtf9O1+XVwkbPbPMSG1LwFQ0OBw3vN0/SBtQJB8EP/FddQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1686577822; a=rsa-sha256; cv=none; b=vRW/Fm6kFTSF08rgZCoLyCyQxp2KkINrQt0yPUiXQY20ZV4xD675W36o8Rl7rbSFoaQTmY 7+ek2fAq+Rno2TpB3wOK9XltHdjTOo6EwlRfp+pDVUsr0eD2e+x7j48UCZ/4ybU4WtbVQp yWszonxjP915chvsHMQ6vCE+iXgY2o1Q1IrIgRhp9FXvbubvCiIRQmce5dp5tFfdS1rXYS jqOC67gK2+XOjwVYq9zmrEUXPEVY9N7kwn2Crumq1KjjmMi+wzmdMRSZ2pgwg8u5yhiNIJ WtIOhnfSXz2EOC22J7ZkgAhfZd4txtmswnErepU7mHm19KFeVzxm0yo3h8+s5w== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4QftNt2Zgzzhww; Mon, 12 Jun 2023 13:50:22 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 35CDoMHC089389; Mon, 12 Jun 2023 13:50:22 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 35CDoMFL089388; Mon, 12 Jun 2023 13:50:22 GMT (envelope-from git) Date: Mon, 12 Jun 2023 13:50:22 GMT Message-Id: <202306121350.35CDoMFL089388@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Mitchell Horne Subject: git: c48ea7b4953e - stable/13 - riscv: MMU detection List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: c48ea7b4953e574905ef2351f421cb33d41fa9c2 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=c48ea7b4953e574905ef2351f421cb33d41fa9c2 commit c48ea7b4953e574905ef2351f421cb33d41fa9c2 Author: Mitchell Horne AuthorDate: 2023-05-22 23:53:43 +0000 Commit: Mitchell Horne CommitDate: 2023-06-12 13:49:54 +0000 riscv: MMU detection Detect and report the supported MMU for each CPU. Export the capabilities to the rest of the kernel and use it in pmap_bootstrap() to check for Sv48 support. Reviewed by: markj MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D39814 (cherry picked from commit 7245ffd10eda4ff604840350943d762f70657983) --- sys/riscv/include/cpu.h | 8 ++++++++ sys/riscv/include/md_var.h | 1 + sys/riscv/riscv/identcpu.c | 30 ++++++++++++++++++++++++++++++ sys/riscv/riscv/pmap.c | 2 +- 4 files changed, 40 insertions(+), 1 deletion(-) diff --git a/sys/riscv/include/cpu.h b/sys/riscv/include/cpu.h index b7d83aa0f25d..d99142bc3c93 100644 --- a/sys/riscv/include/cpu.h +++ b/sys/riscv/include/cpu.h @@ -83,6 +83,14 @@ /* SiFive marchid values */ #define MARCHID_SIFIVE_U7 MARCHID_COMMERCIAL(7) +/* + * MMU virtual-addressing modes. Support for each level implies the previous, + * so Sv48-enabled systems MUST support Sv39, etc. + */ +#define MMU_SV39 0x1 /* 3-level paging */ +#define MMU_SV48 0x2 /* 4-level paging */ +#define MMU_SV57 0x4 /* 5-level paging */ + extern char btext[]; extern char etext[]; diff --git a/sys/riscv/include/md_var.h b/sys/riscv/include/md_var.h index 890f569782a3..687ab9a3a77e 100644 --- a/sys/riscv/include/md_var.h +++ b/sys/riscv/include/md_var.h @@ -40,6 +40,7 @@ extern u_long elf_hwcap; extern register_t mvendorid; extern register_t marchid; extern register_t mimpid; +extern u_int mmu_caps; struct dumperinfo; struct minidumpstate; diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c index 36f7e4a4940a..e1a34983abf7 100644 --- a/sys/riscv/riscv/identcpu.c +++ b/sys/riscv/riscv/identcpu.c @@ -65,10 +65,13 @@ register_t mvendorid; /* The CPU's JEDEC vendor ID */ register_t marchid; /* The architecture ID */ register_t mimpid; /* The implementation ID */ +u_int mmu_caps; + struct cpu_desc { const char *cpu_mvendor_name; const char *cpu_march_name; u_int isa_extensions; /* Single-letter extensions. */ + u_int mmu_caps; }; struct cpu_desc cpu_desc[MAXCPU]; @@ -271,6 +274,20 @@ parse_riscv_isa(struct cpu_desc *desc, char *isa, int len) } #ifdef FDT +static void +parse_mmu_fdt(struct cpu_desc *desc, phandle_t node) +{ + char mmu[16]; + + desc->mmu_caps |= MMU_SV39; + if (OF_getprop(node, "mmu-type", mmu, sizeof(mmu)) > 0) { + if (strcmp(mmu, "riscv,sv48") == 0) + desc->mmu_caps |= MMU_SV48; + else if (strcmp(mmu, "riscv,sv57") == 0) + desc->mmu_caps |= MMU_SV48 | MMU_SV57; + } +} + static void identify_cpu_features_fdt(u_int cpu, struct cpu_desc *desc) { @@ -319,6 +336,9 @@ identify_cpu_features_fdt(u_int cpu, struct cpu_desc *desc) if (parse_riscv_isa(desc, isa, len) != 0) return; + /* Check MMU features. */ + parse_mmu_fdt(desc, node); + /* We are done. */ break; } @@ -358,6 +378,11 @@ update_global_capabilities(u_int cpu, struct cpu_desc *desc) /* Update the capabilities exposed to userspace via AT_HWCAP. */ UPDATE_CAP(elf_hwcap, (u_long)desc->isa_extensions); + /* + * MMU capabilities, e.g. Sv48. + */ + UPDATE_CAP(mmu_caps, desc->mmu_caps); + #undef UPDATE_CAP } @@ -431,6 +456,11 @@ printcpuinfo(u_int cpu) desc->cpu_mvendor_name, desc->cpu_march_name, hart); printf(" marchid=%#lx, mimpid=%#lx\n", marchid, mimpid); + printf(" MMU: %#b\n", desc->mmu_caps, + "\020" + "\01Sv39" + "\02Sv48" + "\03Sv57"); printf(" ISA: %#b\n", desc->isa_extensions, "\020" "\01Atomic" diff --git a/sys/riscv/riscv/pmap.c b/sys/riscv/riscv/pmap.c index a6029f5d642d..19071639def1 100644 --- a/sys/riscv/riscv/pmap.c +++ b/sys/riscv/riscv/pmap.c @@ -713,7 +713,7 @@ pmap_bootstrap(vm_offset_t l1pt, vm_paddr_t kernstart, vm_size_t kernlen) mode = 0; TUNABLE_INT_FETCH("vm.pmap.mode", &mode); - if (mode == PMAP_MODE_SV48) { + if (mode == PMAP_MODE_SV48 && (mmu_caps & MMU_SV48) != 0) { /* * Enable SV48 mode: allocate an L0 page and set SV48 mode in * SATP. If the implementation does not provide SV48 mode,