From nobody Fri Jun 02 19:19:34 2023 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4QXt9L5RWzz4YZCk; Fri, 2 Jun 2023 19:19:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4QXt9L5GLhz41F1; Fri, 2 Jun 2023 19:19:34 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1685733574; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=9KnxwF8sTrMAE2D9UEpa+3G/w7Th16VEf6KqPblDbZA=; b=gl1SrxvLm0HvB93fwAdRfrXybazQrRzttCEjBGVyuoxQT2IC3i9teoKyfkwZapcumkmhjv 66brXCcUjlNSFEjavkIPuBEiM3gfcCBxy3bKVy6ytZdB1n4Up43LES8nxMDaFkTNJiga3g dlRxB5OnVT81kh++yXS6ak9omgvbk/8ho27Y9F4MorIGmDaUTdJ+OJUb26bba8eCljDZ90 mrFo/HzM6CKtPh5djcJhDFiuMOEi98vjBQ0UUBcmtFBJ0SuZDqtc9gEVWI63Yc5fp/B3vy zzkyl5VYtIkks1AGBKf8tKgr+KCRtSAczuOkHarmtC5V5BiaaUVV481+/JQ2Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1685733574; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=9KnxwF8sTrMAE2D9UEpa+3G/w7Th16VEf6KqPblDbZA=; b=wOjGzUqSwTlAZ6ONT/n5Udp9dyccmpx5kb8My2il5Jb7/PC9G6RyH3TClns+5SXJ4UJkNW Jh8/KwGXY2QF5Qou8cJ3BBndq36VPbscOw8m8H4MgKeUpGW+T/8sMAUSnfCscLsHJSL0LD QK7sQFNViU5+SKdjgcLY2nPkw/PtLEie7fi4XxQYYYM1j5fJg8vEqQT6E6LbK/lF6i3E7X OATzydN45D5q3Qk/9XWrADVxuvJRR8J941SAVyMGRdifs2o5NfRlwVylikhveSJBSDJ7aO p30yUnbhE9sWLW7BH8J1i7U3cfDg7m9Fu8GWwLoNLXfcdl0BgtMX8ykRB9vD2A== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1685733574; a=rsa-sha256; cv=none; b=uXI/LjHkaq0ht/rMFleB0tJpENu6GVpD9+cYt5ZjWAgFzx/urjlQesgx3bA+6eg3HzNJID 7o2GOcISZXGWipsbXRFEcHSx1rNzpNr4uK57ngIhUxrlI88HabSQ2UNSwRoOxtDX0TLbPL YrvQS6otk44y5x/mUDK8OK+6V8cFDTPSwr2xYMe5WiDom3v2FJxtkGZQz0Rrj4h7/0TYKF 6vcb/IaTWtGtc0Eksw03M+ebdfK8KKr6dkYBdtprVrfbCagpy0BlUILRfFxMOJvznwERCa XvjaZxCsBRRszZi85gz2G0Td+Hm8cHqXn2XEBLQZZbV/tfbvFRSh2FWKeXQcOw== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4QXt9L4KkLz19h6; Fri, 2 Jun 2023 19:19:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 352JJYsN058001; Fri, 2 Jun 2023 19:19:34 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 352JJYGt058000; Fri, 2 Jun 2023 19:19:34 GMT (envelope-from git) Date: Fri, 2 Jun 2023 19:19:34 GMT Message-Id: <202306021919.352JJYGt058000@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Eric Joyner Subject: git: a138508ef6b0 - stable/13 - ice(4): Update to 1.37.11-k List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: erj X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: a138508ef6b07190904cece1ea29700a731f8b8c Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by erj: URL: https://cgit.FreeBSD.org/src/commit/?id=a138508ef6b07190904cece1ea29700a731f8b8c commit a138508ef6b07190904cece1ea29700a731f8b8c Author: Eric Joyner AuthorDate: 2023-05-24 23:38:02 +0000 Commit: Eric Joyner CommitDate: 2023-06-02 19:14:41 +0000 ice(4): Update to 1.37.11-k This driver update has no corresponding ice_ddp update, and doesn't contain very many functional changes: - Some refactoring for future SR-IOV PF support - Various minor fixes Signed-off-by: Eric Joyner Tested by: jeffrey.e.pieper@intel.com Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D39821 (cherry picked from commit 9dc2f6e26fc24b88f9046667708a5555c63fb461) --- sys/dev/ice/ice_adminq_cmd.h | 3 +- sys/dev/ice/ice_alloc.h | 2 +- sys/dev/ice/ice_bitops.h | 4 +- sys/dev/ice/ice_common.c | 341 +++++++++++++++++++++++----------- sys/dev/ice/ice_common.h | 18 +- sys/dev/ice/ice_common_sysctls.h | 2 +- sys/dev/ice/ice_common_txrx.h | 2 +- sys/dev/ice/ice_controlq.c | 2 +- sys/dev/ice/ice_controlq.h | 2 +- sys/dev/ice/ice_dcb.c | 2 +- sys/dev/ice/ice_dcb.h | 2 +- sys/dev/ice/ice_ddp_common.c | 6 +- sys/dev/ice/ice_ddp_common.h | 8 +- sys/dev/ice/ice_defs.h | 2 +- sys/dev/ice/ice_devids.h | 2 +- sys/dev/ice/ice_drv_info.h | 10 +- sys/dev/ice/ice_features.h | 2 +- sys/dev/ice/ice_flex_pipe.c | 2 +- sys/dev/ice/ice_flex_pipe.h | 2 +- sys/dev/ice/ice_flex_type.h | 2 +- sys/dev/ice/ice_flow.c | 15 +- sys/dev/ice/ice_flow.h | 2 +- sys/dev/ice/ice_fw_logging.c | 2 +- sys/dev/ice/ice_fwlog.c | 2 +- sys/dev/ice/ice_fwlog.h | 2 +- sys/dev/ice/ice_hw_autogen.h | 2 +- sys/dev/ice/ice_iflib.h | 2 +- sys/dev/ice/ice_iflib_recovery_txrx.c | 2 +- sys/dev/ice/ice_iflib_sysctls.h | 2 +- sys/dev/ice/ice_iflib_txrx.c | 2 +- sys/dev/ice/ice_lan_tx_rx.h | 5 +- sys/dev/ice/ice_lib.c | 332 +++++++++++++++++++++++---------- sys/dev/ice/ice_lib.h | 21 ++- sys/dev/ice/ice_nvm.c | 52 ++++-- sys/dev/ice/ice_nvm.h | 2 +- sys/dev/ice/ice_opts.h | 2 +- sys/dev/ice/ice_osdep.c | 2 +- sys/dev/ice/ice_osdep.h | 4 +- sys/dev/ice/ice_protocol_type.h | 41 ++-- sys/dev/ice/ice_rdma.c | 2 +- sys/dev/ice/ice_rdma.h | 2 +- sys/dev/ice/ice_rdma_internal.h | 2 +- sys/dev/ice/ice_resmgr.c | 2 +- sys/dev/ice/ice_resmgr.h | 2 +- sys/dev/ice/ice_rss.h | 2 +- sys/dev/ice/ice_sbq_cmd.h | 2 +- sys/dev/ice/ice_sched.c | 2 +- sys/dev/ice/ice_sched.h | 2 +- sys/dev/ice/ice_status.h | 2 +- sys/dev/ice/ice_strings.c | 2 +- sys/dev/ice/ice_switch.c | 2 +- sys/dev/ice/ice_switch.h | 7 +- sys/dev/ice/ice_type.h | 12 +- sys/dev/ice/ice_vlan_mode.c | 2 +- sys/dev/ice/ice_vlan_mode.h | 2 +- sys/dev/ice/if_ice_iflib.c | 17 +- sys/dev/ice/irdma_di_if.m | 2 +- sys/dev/ice/irdma_if.m | 2 +- sys/dev/ice/virtchnl.h | 105 ++++++++++- sys/dev/ice/virtchnl_inline_ipsec.h | 2 +- 60 files changed, 741 insertions(+), 344 deletions(-) diff --git a/sys/dev/ice/ice_adminq_cmd.h b/sys/dev/ice/ice_adminq_cmd.h index 92ad8055b666..56bfbf27cda2 100644 --- a/sys/dev/ice/ice_adminq_cmd.h +++ b/sys/dev/ice/ice_adminq_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -1987,6 +1987,7 @@ struct ice_aqc_get_port_options { u8 port_options_count; #define ICE_AQC_PORT_OPT_COUNT_S 0 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) +#define ICE_AQC_PORT_OPT_MAX 16 u8 innermost_phy_index; u8 port_options; #define ICE_AQC_PORT_OPT_ACTIVE_S 0 diff --git a/sys/dev/ice/ice_alloc.h b/sys/dev/ice/ice_alloc.h index bfcb376d45b2..d84be78b4bc2 100644 --- a/sys/dev/ice/ice_alloc.h +++ b/sys/dev/ice/ice_alloc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_bitops.h b/sys/dev/ice/ice_bitops.h index c29963d0a318..e7b8b19cfe8a 100644 --- a/sys/dev/ice/ice_bitops.h +++ b/sys/dev/ice/ice_bitops.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -461,7 +461,7 @@ ice_bitmap_hweight(ice_bitmap_t *bm, u16 size) } /** - * ice_cmp_bitmaps - compares two bitmaps. + * ice_cmp_bitmap - compares two bitmaps. * @bmp1: the bitmap to compare * @bmp2: the bitmap to compare with bmp1 * @size: Size of the bitmaps in bits diff --git a/sys/dev/ice/ice_common.c b/sys/dev/ice/ice_common.c index c2efddeb4f7c..e4c112d3a3c2 100644 --- a/sys/dev/ice/ice_common.c +++ b/sys/dev/ice/ice_common.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -37,81 +37,81 @@ #include "ice_flow.h" #include "ice_switch.h" -#define ICE_PF_RESET_WAIT_COUNT 300 +#define ICE_PF_RESET_WAIT_COUNT 500 static const char * const ice_link_mode_str_low[] = { - [0] = "100BASE_TX", - [1] = "100M_SGMII", - [2] = "1000BASE_T", - [3] = "1000BASE_SX", - [4] = "1000BASE_LX", - [5] = "1000BASE_KX", - [6] = "1G_SGMII", - [7] = "2500BASE_T", - [8] = "2500BASE_X", - [9] = "2500BASE_KX", - [10] = "5GBASE_T", - [11] = "5GBASE_KR", - [12] = "10GBASE_T", - [13] = "10G_SFI_DA", - [14] = "10GBASE_SR", - [15] = "10GBASE_LR", - [16] = "10GBASE_KR_CR1", - [17] = "10G_SFI_AOC_ACC", - [18] = "10G_SFI_C2C", - [19] = "25GBASE_T", - [20] = "25GBASE_CR", - [21] = "25GBASE_CR_S", - [22] = "25GBASE_CR1", - [23] = "25GBASE_SR", - [24] = "25GBASE_LR", - [25] = "25GBASE_KR", - [26] = "25GBASE_KR_S", - [27] = "25GBASE_KR1", - [28] = "25G_AUI_AOC_ACC", - [29] = "25G_AUI_C2C", - [30] = "40GBASE_CR4", - [31] = "40GBASE_SR4", - [32] = "40GBASE_LR4", - [33] = "40GBASE_KR4", - [34] = "40G_XLAUI_AOC_ACC", - [35] = "40G_XLAUI", - [36] = "50GBASE_CR2", - [37] = "50GBASE_SR2", - [38] = "50GBASE_LR2", - [39] = "50GBASE_KR2", - [40] = "50G_LAUI2_AOC_ACC", - [41] = "50G_LAUI2", - [42] = "50G_AUI2_AOC_ACC", - [43] = "50G_AUI2", - [44] = "50GBASE_CP", - [45] = "50GBASE_SR", - [46] = "50GBASE_FR", - [47] = "50GBASE_LR", - [48] = "50GBASE_KR_PAM4", - [49] = "50G_AUI1_AOC_ACC", - [50] = "50G_AUI1", - [51] = "100GBASE_CR4", - [52] = "100GBASE_SR4", - [53] = "100GBASE_LR4", - [54] = "100GBASE_KR4", - [55] = "100G_CAUI4_AOC_ACC", - [56] = "100G_CAUI4", - [57] = "100G_AUI4_AOC_ACC", - [58] = "100G_AUI4", - [59] = "100GBASE_CR_PAM4", - [60] = "100GBASE_KR_PAM4", - [61] = "100GBASE_CP2", - [62] = "100GBASE_SR2", - [63] = "100GBASE_DR", + ice_arr_elem_idx(0, "100BASE_TX"), + ice_arr_elem_idx(1, "100M_SGMII"), + ice_arr_elem_idx(2, "1000BASE_T"), + ice_arr_elem_idx(3, "1000BASE_SX"), + ice_arr_elem_idx(4, "1000BASE_LX"), + ice_arr_elem_idx(5, "1000BASE_KX"), + ice_arr_elem_idx(6, "1G_SGMII"), + ice_arr_elem_idx(7, "2500BASE_T"), + ice_arr_elem_idx(8, "2500BASE_X"), + ice_arr_elem_idx(9, "2500BASE_KX"), + ice_arr_elem_idx(10, "5GBASE_T"), + ice_arr_elem_idx(11, "5GBASE_KR"), + ice_arr_elem_idx(12, "10GBASE_T"), + ice_arr_elem_idx(13, "10G_SFI_DA"), + ice_arr_elem_idx(14, "10GBASE_SR"), + ice_arr_elem_idx(15, "10GBASE_LR"), + ice_arr_elem_idx(16, "10GBASE_KR_CR1"), + ice_arr_elem_idx(17, "10G_SFI_AOC_ACC"), + ice_arr_elem_idx(18, "10G_SFI_C2C"), + ice_arr_elem_idx(19, "25GBASE_T"), + ice_arr_elem_idx(20, "25GBASE_CR"), + ice_arr_elem_idx(21, "25GBASE_CR_S"), + ice_arr_elem_idx(22, "25GBASE_CR1"), + ice_arr_elem_idx(23, "25GBASE_SR"), + ice_arr_elem_idx(24, "25GBASE_LR"), + ice_arr_elem_idx(25, "25GBASE_KR"), + ice_arr_elem_idx(26, "25GBASE_KR_S"), + ice_arr_elem_idx(27, "25GBASE_KR1"), + ice_arr_elem_idx(28, "25G_AUI_AOC_ACC"), + ice_arr_elem_idx(29, "25G_AUI_C2C"), + ice_arr_elem_idx(30, "40GBASE_CR4"), + ice_arr_elem_idx(31, "40GBASE_SR4"), + ice_arr_elem_idx(32, "40GBASE_LR4"), + ice_arr_elem_idx(33, "40GBASE_KR4"), + ice_arr_elem_idx(34, "40G_XLAUI_AOC_ACC"), + ice_arr_elem_idx(35, "40G_XLAUI"), + ice_arr_elem_idx(36, "50GBASE_CR2"), + ice_arr_elem_idx(37, "50GBASE_SR2"), + ice_arr_elem_idx(38, "50GBASE_LR2"), + ice_arr_elem_idx(39, "50GBASE_KR2"), + ice_arr_elem_idx(40, "50G_LAUI2_AOC_ACC"), + ice_arr_elem_idx(41, "50G_LAUI2"), + ice_arr_elem_idx(42, "50G_AUI2_AOC_ACC"), + ice_arr_elem_idx(43, "50G_AUI2"), + ice_arr_elem_idx(44, "50GBASE_CP"), + ice_arr_elem_idx(45, "50GBASE_SR"), + ice_arr_elem_idx(46, "50GBASE_FR"), + ice_arr_elem_idx(47, "50GBASE_LR"), + ice_arr_elem_idx(48, "50GBASE_KR_PAM4"), + ice_arr_elem_idx(49, "50G_AUI1_AOC_ACC"), + ice_arr_elem_idx(50, "50G_AUI1"), + ice_arr_elem_idx(51, "100GBASE_CR4"), + ice_arr_elem_idx(52, "100GBASE_SR4"), + ice_arr_elem_idx(53, "100GBASE_LR4"), + ice_arr_elem_idx(54, "100GBASE_KR4"), + ice_arr_elem_idx(55, "100G_CAUI4_AOC_ACC"), + ice_arr_elem_idx(56, "100G_CAUI4"), + ice_arr_elem_idx(57, "100G_AUI4_AOC_ACC"), + ice_arr_elem_idx(58, "100G_AUI4"), + ice_arr_elem_idx(59, "100GBASE_CR_PAM4"), + ice_arr_elem_idx(60, "100GBASE_KR_PAM4"), + ice_arr_elem_idx(61, "100GBASE_CP2"), + ice_arr_elem_idx(62, "100GBASE_SR2"), + ice_arr_elem_idx(63, "100GBASE_DR"), }; static const char * const ice_link_mode_str_high[] = { - [0] = "100GBASE_KR2_PAM4", - [1] = "100G_CAUI2_AOC_ACC", - [2] = "100G_CAUI2", - [3] = "100G_AUI2_AOC_ACC", - [4] = "100G_AUI2", + ice_arr_elem_idx(0, "100GBASE_KR2_PAM4"), + ice_arr_elem_idx(1, "100G_CAUI2_AOC_ACC"), + ice_arr_elem_idx(2, "100G_CAUI2"), + ice_arr_elem_idx(3, "100G_AUI2_AOC_ACC"), + ice_arr_elem_idx(4, "100G_AUI2"), }; /** @@ -1292,7 +1292,7 @@ static enum ice_status ice_pf_reset(struct ice_hw *hw) * that is occurring during a download package operation. */ for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + - ICE_PF_RESET_WAIT_COUNT; cnt++) { + ICE_PF_RESET_WAIT_COUNT; cnt++) { reg = rd32(hw, PFGEN_CTRL); if (!(reg & PFGEN_CTRL_PFSWR_M)) break; @@ -1378,6 +1378,37 @@ ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) return ICE_SUCCESS; } +/** + * ice_copy_rxq_ctx_from_hw - Copy rxq context register from HW + * @hw: pointer to the hardware structure + * @ice_rxq_ctx: pointer to the rxq context + * @rxq_index: the index of the Rx queue + * + * Copies rxq context from HW register space to dense structure + */ +static enum ice_status +ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) +{ + u8 i; + + if (!ice_rxq_ctx) + return ICE_ERR_BAD_PTR; + + if (rxq_index > QRX_CTRL_MAX_INDEX) + return ICE_ERR_PARAM; + + /* Copy each dword separately from HW */ + for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { + u32 *ctx = (u32 *)(ice_rxq_ctx + (i * sizeof(u32))); + + *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); + + ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); + } + + return ICE_SUCCESS; +} + /* LAN Rx Queue Context */ static const struct ice_ctx_ele ice_rlan_ctx_info[] = { /* Field Width LSB */ @@ -1429,6 +1460,32 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); } +/** + * ice_read_rxq_ctx - Read rxq context from HW + * @hw: pointer to the hardware structure + * @rlan_ctx: pointer to the rxq context + * @rxq_index: the index of the Rx queue + * + * Read rxq context from HW register space and then converts it from dense + * structure to sparse + */ +enum ice_status +ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, + u32 rxq_index) +{ + u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; + enum ice_status status; + + if (!rlan_ctx) + return ICE_ERR_BAD_PTR; + + status = ice_copy_rxq_ctx_from_hw(hw, ctx_buf, rxq_index); + if (status) + return status; + + return ice_get_ctx(ctx_buf, (u8 *)rlan_ctx, ice_rlan_ctx_info); +} + /** * ice_clear_rxq_ctx * @hw: pointer to the hardware structure @@ -1450,7 +1507,9 @@ enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) return ICE_SUCCESS; } -/* LAN Tx Queue Context */ +/* LAN Tx Queue Context used for set Tx config by ice_aqc_opc_add_txqs, + * Bit[0-175] is valid + */ const struct ice_ctx_ele ice_tlan_ctx_info[] = { /* Field Width LSB */ ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), @@ -3041,7 +3100,6 @@ enum ice_status ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, bool save_bad_pac, bool pad_short_pac, bool double_vlan, struct ice_sq_cd *cd) - { struct ice_aqc_set_port_params *cmd; struct ice_hw *hw = pi->hw; @@ -3093,8 +3151,8 @@ bool ice_is_100m_speed_supported(struct ice_hw *hw) * Note: In the structure of [phy_type_low, phy_type_high], there should * be one bit set, as this function will convert one PHY type to its * speed. - * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned - * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned + * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned + * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned */ static u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) @@ -4772,7 +4830,7 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, * @ce_info: a description of the struct to be filled */ static void -ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u8 dest_byte, mask; u8 *src, *target; @@ -4790,7 +4848,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); - dest_byte &= ~(mask); + dest_byte &= mask; dest_byte >>= shift_width; @@ -4808,7 +4866,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u16 dest_word, mask; u8 *src, *target; @@ -4830,7 +4888,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) /* the data in the memory is stored as little endian so mask it * correctly */ - src_word &= ~(CPU_TO_LE16(mask)); + src_word &= CPU_TO_LE16(mask); /* get the data back into host order before shifting */ dest_word = LE16_TO_CPU(src_word); @@ -4851,7 +4909,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u32 dest_dword, mask; __le32 src_dword; @@ -4881,7 +4939,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) /* the data in the memory is stored as little endian so mask it * correctly */ - src_dword &= ~(CPU_TO_LE32(mask)); + src_dword &= CPU_TO_LE32(mask); /* get the data back into host order before shifting */ dest_dword = LE32_TO_CPU(src_dword); @@ -4902,7 +4960,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u64 dest_qword, mask; __le64 src_qword; @@ -4932,7 +4990,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) /* the data in the memory is stored as little endian so mask it * correctly */ - src_qword &= ~(CPU_TO_LE64(mask)); + src_qword &= CPU_TO_LE64(mask); /* get the data back into host order before shifting */ dest_qword = LE64_TO_CPU(src_qword); @@ -4953,7 +5011,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the structure to be read from */ enum ice_status -ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { int f; @@ -5789,7 +5847,7 @@ enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) } /** - * ice_cfg_get_cur_lldp_persist_status + * ice_get_cur_lldp_persist_status * @hw: pointer to the HW struct * @lldp_status: return value of LLDP persistent status * @@ -6266,6 +6324,8 @@ ice_aq_set_health_status_config(struct ice_hw *hw, u8 event_source, * when PF owns more than 1 port it must be true * @active_option_idx: index of active port option in returned buffer * @active_option_valid: active option in returned buffer is valid + * @pending_option_idx: index of pending port option in returned buffer + * @pending_option_valid: pending option in returned buffer is valid * * Calls Get Port Options AQC (0x06ea) and verifies result. */ @@ -6273,17 +6333,14 @@ enum ice_status ice_aq_get_port_options(struct ice_hw *hw, struct ice_aqc_get_port_options_elem *options, u8 *option_count, u8 lport, bool lport_valid, - u8 *active_option_idx, bool *active_option_valid) + u8 *active_option_idx, bool *active_option_valid, + u8 *pending_option_idx, bool *pending_option_valid) { struct ice_aqc_get_port_options *cmd; struct ice_aq_desc desc; enum ice_status status; - u8 pmd_count; - u8 max_speed; u8 i; - ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); - /* options buffer shall be able to hold max returned options */ if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) return ICE_ERR_PARAM; @@ -6291,8 +6348,7 @@ ice_aq_get_port_options(struct ice_hw *hw, cmd = &desc.params.get_port_options; ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); - if (lport_valid) - cmd->lport_num = lport; + cmd->lport_num = lport; cmd->lport_num_valid = lport_valid; status = ice_aq_send_cmd(hw, &desc, options, @@ -6313,34 +6369,59 @@ ice_aq_get_port_options(struct ice_hw *hw, *active_option_idx); } - /* verify indirect FW response & mask output options fields */ + *pending_option_valid = cmd->pending_port_option_status & + ICE_AQC_PENDING_PORT_OPT_VALID; + if (*pending_option_valid) { + *pending_option_idx = cmd->pending_port_option_status & + ICE_AQC_PENDING_PORT_OPT_IDX_M; + if (*pending_option_idx > (*option_count - 1)) + return ICE_ERR_OUT_OF_RANGE; + ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", + *pending_option_idx); + } + + /* mask output options fields */ for (i = 0; i < *option_count; i++) { options[i].pmd &= ICE_AQC_PORT_OPT_PMD_COUNT_M; options[i].max_lane_speed &= ICE_AQC_PORT_OPT_MAX_LANE_M; - pmd_count = options[i].pmd; - max_speed = options[i].max_lane_speed; ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", - pmd_count, max_speed); - - /* check only entries containing valid max pmd speed values, - * other reserved values may be returned, when logical port - * used is unrelated to specific option - */ - if (max_speed <= ICE_AQC_PORT_OPT_MAX_LANE_100G) { - if (pmd_count > ICE_MAX_PORT_PER_PCI_DEV) - return ICE_ERR_OUT_OF_RANGE; - if (pmd_count > 2 && - max_speed > ICE_AQC_PORT_OPT_MAX_LANE_25G) - return ICE_ERR_CFG; - if (pmd_count > 7 && - max_speed > ICE_AQC_PORT_OPT_MAX_LANE_10G) - return ICE_ERR_CFG; - } + options[i].pmd, options[i].max_lane_speed); } return ICE_SUCCESS; } +/** + * ice_aq_set_port_option + * @hw: pointer to the hw struct + * @lport: logical port to call the command with + * @lport_valid: when false, FW uses port owned by the PF instead of lport, + * when PF owns more than 1 port it must be true + * @new_option: new port option to be written + * + * Calls Set Port Options AQC (0x06eb). + */ +enum ice_status +ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, + u8 new_option) +{ + struct ice_aqc_set_port_option *cmd; + struct ice_aq_desc desc; + + if (new_option >= ICE_AQC_PORT_OPT_COUNT_M) + return ICE_ERR_PARAM; + + cmd = &desc.params.set_port_option; + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); + + cmd->lport_num = lport; + + cmd->lport_num_valid = lport_valid; + cmd->selected_port_option = new_option; + + return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); +} + /** * ice_aq_set_lldp_mib - Set the LLDP MIB * @hw: pointer to the HW struct @@ -6440,6 +6521,42 @@ bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) ICE_FW_API_REPORT_DFLT_CFG_PATCH); } +/* each of the indexes into the following array match the speed of a return + * value from the list of AQ returned speeds like the range: + * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding + * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) The array is defined as 15 + * elements long because the link_speed returned by the firmware is a 16 bit + * value, but is indexed by [fls(speed) - 1] + */ +static const u32 ice_aq_to_link_speed[15] = { + ICE_LINK_SPEED_10MBPS, /* BIT(0) */ + ICE_LINK_SPEED_100MBPS, + ICE_LINK_SPEED_1000MBPS, + ICE_LINK_SPEED_2500MBPS, + ICE_LINK_SPEED_5000MBPS, + ICE_LINK_SPEED_10000MBPS, + ICE_LINK_SPEED_20000MBPS, + ICE_LINK_SPEED_25000MBPS, + ICE_LINK_SPEED_40000MBPS, + ICE_LINK_SPEED_50000MBPS, + ICE_LINK_SPEED_100000MBPS, /* BIT(10) */ + ICE_LINK_SPEED_UNKNOWN, + ICE_LINK_SPEED_UNKNOWN, + ICE_LINK_SPEED_UNKNOWN, + ICE_LINK_SPEED_UNKNOWN /* BIT(14) */ +}; + +/** + * ice_get_link_speed - get integer speed from table + * @index: array index from fls(aq speed) - 1 + * + * Returns: u32 value containing integer speed + */ +u32 ice_get_link_speed(u16 index) +{ + return ice_aq_to_link_speed[index]; +} + /** * ice_fw_supports_fec_dis_auto * @hw: pointer to the hardware structure diff --git a/sys/dev/ice/ice_common.h b/sys/dev/ice/ice_common.h index 73e051fdda67..01ed55c192a1 100644 --- a/sys/dev/ice/ice_common.h +++ b/sys/dev/ice/ice_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -57,7 +57,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw); void ice_deinit_hw(struct ice_hw *hw); enum ice_status ice_check_reset(struct ice_hw *hw); enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); - enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); @@ -85,7 +84,6 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, struct ice_aq_desc *desc, void *buf, u16 buf_size, struct ice_sq_cd *cd); void ice_clear_pxe_mode(struct ice_hw *hw); - enum ice_status ice_get_caps(struct ice_hw *hw); void ice_set_safe_mode_caps(struct ice_hw *hw); @@ -109,9 +107,14 @@ enum ice_status ice_set_mac_type(struct ice_hw *hw); */ #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) +#define ice_arr_elem_idx(idx, val) [(idx)] = (val) + enum ice_status ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, u32 rxq_index); +enum ice_status +ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, + u32 rxq_index); enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); enum ice_status ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); @@ -159,6 +162,8 @@ extern const struct ice_ctx_ele ice_tlan_ctx_info[]; enum ice_status ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); +enum ice_status +ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); enum ice_status ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, @@ -240,6 +245,7 @@ enum ice_status ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, bool write, struct ice_sq_cd *cd); +u32 ice_get_link_speed(u16 index); enum ice_status ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, @@ -255,9 +261,11 @@ enum ice_status ice_aq_get_port_options(struct ice_hw *hw, struct ice_aqc_get_port_options_elem *options, u8 *option_count, u8 lport, bool lport_valid, - u8 *active_option_idx, bool *active_option_valid); + u8 *active_option_idx, bool *active_option_valid, + u8 *pending_option_idx, bool *pending_option_valid); enum ice_status -ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); +ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, + u8 new_option); enum ice_status __ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data); enum ice_status diff --git a/sys/dev/ice/ice_common_sysctls.h b/sys/dev/ice/ice_common_sysctls.h index 11cfc50848f5..98a1bd6f8df6 100644 --- a/sys/dev/ice/ice_common_sysctls.h +++ b/sys/dev/ice/ice_common_sysctls.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_common_txrx.h b/sys/dev/ice/ice_common_txrx.h index dd2b3c5bff0d..4797fe86b835 100644 --- a/sys/dev/ice/ice_common_txrx.h +++ b/sys/dev/ice/ice_common_txrx.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_controlq.c b/sys/dev/ice/ice_controlq.c index 76de98dcfafc..aeb651b45fa8 100644 --- a/sys/dev/ice/ice_controlq.c +++ b/sys/dev/ice/ice_controlq.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_controlq.h b/sys/dev/ice/ice_controlq.h index 16d47ae77f8f..c556fcd20255 100644 --- a/sys/dev/ice/ice_controlq.h +++ b/sys/dev/ice/ice_controlq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_dcb.c b/sys/dev/ice/ice_dcb.c index 19ab0d349cf7..244566bca308 100644 --- a/sys/dev/ice/ice_dcb.c +++ b/sys/dev/ice/ice_dcb.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_dcb.h b/sys/dev/ice/ice_dcb.h index 504a356221c5..d3f371deed4f 100644 --- a/sys/dev/ice/ice_dcb.h +++ b/sys/dev/ice/ice_dcb.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_ddp_common.c b/sys/dev/ice/ice_ddp_common.c index 730b78b0f81e..91dde8666153 100644 --- a/sys/dev/ice/ice_ddp_common.c +++ b/sys/dev/ice/ice_ddp_common.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -1470,14 +1470,14 @@ struct ice_buf_build *ice_pkg_buf_alloc(struct ice_hw *hw) return bld; } -static bool ice_is_gtp_u_profile(u16 prof_idx) +static bool ice_is_gtp_u_profile(u32 prof_idx) { return (prof_idx >= ICE_PROFID_IPV6_GTPU_TEID && prof_idx <= ICE_PROFID_IPV6_GTPU_IPV6_TCP) || prof_idx == ICE_PROFID_IPV4_GTPU_TEID; } -static bool ice_is_gtp_c_profile(u16 prof_idx) +static bool ice_is_gtp_c_profile(u32 prof_idx) { switch (prof_idx) { case ICE_PROFID_IPV4_GTPC_TEID: diff --git a/sys/dev/ice/ice_ddp_common.h b/sys/dev/ice/ice_ddp_common.h index 621729b03446..f59c0a614888 100644 --- a/sys/dev/ice/ice_ddp_common.h +++ b/sys/dev/ice/ice_ddp_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,8 +30,8 @@ */ /*$FreeBSD$*/ -#ifndef _ICE_DDP_H_ -#define _ICE_DDP_H_ +#ifndef _ICE_DDP_COMMON_H_ +#define _ICE_DDP_COMMON_H_ #include "ice_osdep.h" #include "ice_adminq_cmd.h" @@ -475,4 +475,4 @@ void ice_pkg_buf_free(struct ice_hw *hw, struct ice_buf_build *bld); enum ice_status ice_cfg_tx_topo(struct ice_hw *hw, u8 *buf, u32 len); -#endif /* _ICE_DDP_H_ */ +#endif /* _ICE_DDP_COMMON_H_ */ diff --git a/sys/dev/ice/ice_defs.h b/sys/dev/ice/ice_defs.h index 8a1dda2c492c..5205a3d9b492 100644 --- a/sys/dev/ice/ice_defs.h +++ b/sys/dev/ice/ice_defs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_devids.h b/sys/dev/ice/ice_devids.h index dc8970952b49..1048da7ac5de 100644 --- a/sys/dev/ice/ice_devids.h +++ b/sys/dev/ice/ice_devids.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_drv_info.h b/sys/dev/ice/ice_drv_info.h index f47adb1572c6..407b6d555130 100644 --- a/sys/dev/ice/ice_drv_info.h +++ b/sys/dev/ice/ice_drv_info.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -63,16 +63,16 @@ * @var ice_rc_version * @brief driver release candidate version number */ -const char ice_driver_version[] = "1.37.7-k"; +const char ice_driver_version[] = "1.37.11-k"; const uint8_t ice_major_version = 1; const uint8_t ice_minor_version = 37; -const uint8_t ice_patch_version = 7; +const uint8_t ice_patch_version = 11; const uint8_t ice_rc_version = 0; #define PVIDV(vendor, devid, name) \ - PVID(vendor, devid, name " - 1.37.7-k") + PVID(vendor, devid, name " - 1.37.11-k") #define PVIDV_OEM(vendor, devid, svid, sdevid, revid, name) \ - PVID_OEM(vendor, devid, svid, sdevid, revid, name " - 1.37.7-k") + PVID_OEM(vendor, devid, svid, sdevid, revid, name " - 1.37.11-k") /** * @var ice_vendor_info_array diff --git a/sys/dev/ice/ice_features.h b/sys/dev/ice/ice_features.h index efbeb12c3ab1..24404434d162 100644 --- a/sys/dev/ice/ice_features.h +++ b/sys/dev/ice/ice_features.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_flex_pipe.c b/sys/dev/ice/ice_flex_pipe.c index 36c420478131..5a6a77a65c43 100644 --- a/sys/dev/ice/ice_flex_pipe.c +++ b/sys/dev/ice/ice_flex_pipe.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_flex_pipe.h b/sys/dev/ice/ice_flex_pipe.h index ada71b2d446a..a20be014763b 100644 --- a/sys/dev/ice/ice_flex_pipe.h +++ b/sys/dev/ice/ice_flex_pipe.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_flex_type.h b/sys/dev/ice/ice_flex_type.h index 145797f34b7a..56587e890a0f 100644 --- a/sys/dev/ice/ice_flex_type.h +++ b/sys/dev/ice/ice_flex_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/ice/ice_flow.c b/sys/dev/ice/ice_flow.c index 73abf03d43b8..954ca84175db 100644 --- a/sys/dev/ice/ice_flow.c +++ b/sys/dev/ice/ice_flow.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022, Intel Corporation +/* Copyright (c) 2023, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -1368,6 +1368,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) const enum ice_block blk = ICE_BLK_RSS; struct ice_flow_prof *p, *t; enum ice_status status = ICE_SUCCESS; + u16 vsig; if (!ice_is_vsi_valid(hw, vsi_handle)) return ICE_ERR_PARAM; @@ -1377,7 +1378,16 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) ice_acquire_lock(&hw->rss_locks); LIST_FOR_EACH_ENTRY_SAFE(p, t, &hw->fl_profs[blk], ice_flow_prof, - l_entry) + l_entry) { + int ret; + + /* check if vsig is already removed */ + ret = ice_vsig_find_vsi(hw, blk, + ice_get_hw_vsi_num(hw, vsi_handle), + &vsig); + if (!ret && !vsig) + break; *** 1430 LINES SKIPPED ***