From nobody Thu Jan 26 18:35:29 2023 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4P2qC54FcTz3bLns; Thu, 26 Jan 2023 18:35:29 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4P2qC53n6Tz43RL; Thu, 26 Jan 2023 18:35:29 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1674758129; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Q92UHr9uJeRzq/b8+fWgXpMF//e85sJUYuC9LtFpkT8=; b=ltYfBYvSHihX9VDh5yHxHpVbuOQ0zzlHh7yVSTBZFSm+6WgWICl7yYD21PnFx0/g928udx 5JJ205NykuIVg2Anm7sr7BQ4ps6Barg4hpqCX8utI3BovYuYt1mkLckMslOXo60HWNd2/G UGF2oT+GHTN4ZNwkxev+aBTcVxsqP2jbMycSuM1aHu0l7DrwMDCRXErwcv1vHoiAIvF/vH 23WjwYqnaxQkEG4yOC7e9CWfxfpwd4BuM0hSLOC8TgqlJLqY6UyFOztqhS/T1M8cLr0DvR v0SK1VBXA+x1ImrciXn90v90pk7fzEVLNZVe7rMHR8rovIyqVOBAiquGAY/0nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1674758129; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Q92UHr9uJeRzq/b8+fWgXpMF//e85sJUYuC9LtFpkT8=; b=sDYQ9Fd2qAUvdT8T+3ZauaTc5nuKbkhKBAKQbJONWmZydPyDXD8XtqdH/xcOTaNesHWhHx uOCgjqodauR+UPCo6+18JuEGUqB1ogGYU5ByN7PqGwsUBgLrI26XBX/K+z+c9cqmdmiMkl 2E9E54P+rgOHpwIQY8JFh+NOa2Cl4AMFg//8WOrNkqhU/+pMqE1cKGw/TXbsmxERy9EJBC Oaq4e6pJRrn3PDLnaYsMTZNfJMFO4PGkV2NSblTayjtJKuQg+yPA9Nz5pC8Di8KtDAowRY sDT48X6SG9ByToDFMinI0bltdvUJnpq5hf7uMAnZTMKQNfP2q2CrGweT6TYLBQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1674758129; a=rsa-sha256; cv=none; b=Wd0DsW4YdrO6OelFuV576STkxt53sVt1+2uMkgZ5CRx7twcyk20XTMo7vLehTyajuI1Fry PJwyslQBP2OAYt1oyhSkjwthRM/Bx9gObBNqoa2ul/tqe/8aru7qCa67vlWDgd6TauBisS S+C+4OmfAICfNs6pSxj6wtu3L593tnx0yec3yHrMVO5FrYcIDGMF9Z9SXAJnPhZeFw8emR eznO8I7DkkeQJE48PLgy0hIRczG8ODHV0ugJ2WmwR4PvxR/2cwe3L0JetWNUauatopplDu lyCwYfBcUvBvFwgeQYClRXp7vhuxLg+edlGBys3bzZZcYlYkmCoOg02PMhYI+Q== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4P2qC52t64zfrR; Thu, 26 Jan 2023 18:35:29 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 30QIZTKr005641; Thu, 26 Jan 2023 18:35:29 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 30QIZTIe005640; Thu, 26 Jan 2023 18:35:29 GMT (envelope-from git) Date: Thu, 26 Jan 2023 18:35:29 GMT Message-Id: <202301261835.30QIZTIe005640@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: John Baldwin Subject: git: 38433b790de0 - stable/13 - bhyve/ioapic: improve the tracking of IRR bit List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jhb X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: 38433b790de01eabc39c53caf3a0c84921fecda6 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by jhb: URL: https://cgit.FreeBSD.org/src/commit/?id=38433b790de01eabc39c53caf3a0c84921fecda6 commit 38433b790de01eabc39c53caf3a0c84921fecda6 Author: Roger Pau Monné AuthorDate: 2021-01-19 11:52:28 +0000 Commit: John Baldwin CommitDate: 2023-01-26 18:34:04 +0000 bhyve/ioapic: improve the tracking of IRR bit One common method of EOI'ing an interrupt at the IO-APIC level is to switch the pin to edge triggering mode and then back into level mode. That would cause the IRR bit to be cleared and thus further interrupts to be injected. FreeBSD does indeed use that method if the IO-APIC EOI register is not supported. The bhyve IO-APIC emulation code didn't clear the IRR bit when doing that switch, and was also missing acknowledging the IRR state when trying to inject an interrupt in vioapic_send_intr. Reviewed by: grehan Differential revision: https://reviews.freebsd.org/D28238 (cherry picked from commit 5ea878684f6cfff4ad05186346ff3a4828d980ca) --- sys/amd64/vmm/io/vioapic.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/sys/amd64/vmm/io/vioapic.c b/sys/amd64/vmm/io/vioapic.c index 941f7c7364bc..639c1b07eb08 100644 --- a/sys/amd64/vmm/io/vioapic.c +++ b/sys/amd64/vmm/io/vioapic.c @@ -122,8 +122,14 @@ vioapic_send_intr(struct vioapic *vioapic, int pin) phys = ((low & IOART_DESTMOD) == IOART_DESTPHY); delmode = low & IOART_DELMOD; level = low & IOART_TRGRLVL ? true : false; - if (level) + if (level) { + if ((low & IOART_REM_IRR) != 0) { + VIOAPIC_CTR1(vioapic, "ioapic pin%d: irr pending", + pin); + return; + } vioapic->rtbl[pin].reg |= IOART_REM_IRR; + } vector = low & IOART_INTVEC; dest = high >> APIC_ID_SHIFT; @@ -342,6 +348,16 @@ vioapic_write(struct vioapic *vioapic, int vcpuid, uint32_t addr, uint32_t data) vioapic->rtbl[pin].reg &= ~mask64 | RTBL_RO_BITS; vioapic->rtbl[pin].reg |= data64 & ~RTBL_RO_BITS; + /* + * Switching from level to edge triggering will clear the IRR + * bit. This is what FreeBSD will do in order to EOI an + * interrupt when the IO-APIC doesn't support targeted EOI (see + * _ioapic_eoi_source). + */ + if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGREDG && + (vioapic->rtbl[pin].reg & IOART_REM_IRR) != 0) + vioapic->rtbl[pin].reg &= ~IOART_REM_IRR; + VIOAPIC_CTR2(vioapic, "ioapic pin%d: redir table entry %#lx", pin, vioapic->rtbl[pin].reg); @@ -363,12 +379,10 @@ vioapic_write(struct vioapic *vioapic, int vcpuid, uint32_t addr, uint32_t data) /* * Generate an interrupt if the following conditions are met: - * - previous interrupt has been EOIed * - pin trigger mode is level * - pin level is asserted */ - if ((vioapic->rtbl[pin].reg & IOART_REM_IRR) == 0 && - (vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGRLVL && + if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGRLVL && (vioapic->rtbl[pin].acnt > 0)) { VIOAPIC_CTR2(vioapic, "ioapic pin%d: asserted at rtbl " "write, acnt %d", pin, vioapic->rtbl[pin].acnt);