git: 7fcb2a0b7932 - stable/13 - Add more arm64 hypervisor registers

The branch stable/13 has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=7fcb2a0b7932f01804a79a7cbb8b09180c16720e

commit 7fcb2a0b7932f01804a79a7cbb8b09180c16720e
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2022-11-14 15:42:51 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2023-01-23 12:36:28 +0000

    Add more arm64 hypervisor registers
    
    These will be used by bhyve.
    
    Sponsored by:   Innovate UK
    Sponsored by:   The FreeBSD Foundation
    
    (cherry picked from commit 2468c61958f5e50927775f0611b44402a461840d)
---
 sys/arm64/include/hypervisor.h | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index dc6ccbfe20a9..84abe17f310e 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -119,6 +119,11 @@
 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */
 #define	HPFAR_EL2_FIPA_SHIFT	4
 #define	HPFAR_EL2_FIPA_MASK	0xfffffffff0
+#define	HPFAR_EL2_FIPA_GET(x)	\
+    (((x) & HPFAR_EL2_FIPA_MASK) >> HPFAR_EL2_FIPA_SHIFT)
+/* HPFAR_EL2_FIPA holds the 4k page address */
+#define	HPFAR_EL2_FIPA_ADDR(x)	\
+    (HPFAR_EL2_FIPA_GET(x) << 12)
 
 /* ICC_SRE_EL2 */
 #define	ICC_SRE_EL2_SRE		(1UL << 0)
@@ -149,12 +154,18 @@
 /* Bits 7:6 are reserved */
 #define	TCR_EL2_IRGN0_SHIFT	8
 #define	TCR_EL2_IRGN0_MASK	(0x3UL << TCR_EL2_IRGN0_SHIFT)
+#define	TCR_EL2_IRGN0_WBWA	(1UL << TCR_EL2_IRGN0_SHIFT)
 #define	TCR_EL2_ORGN0_SHIFT	10
 #define	TCR_EL2_ORGN0_MASK	(0x3UL << TCR_EL2_ORGN0_SHIFT)
+#define	TCR_EL2_ORGN0_WBWA	(1UL << TCR_EL2_ORGN0_SHIFT)
 #define	TCR_EL2_SH0_SHIFT	12
 #define	TCR_EL2_SH0_MASK	(0x3UL << TCR_EL2_SH0_SHIFT)
+#define	TCR_EL2_SH0_IS		(3UL << TCR_EL2_SH0_SHIFT)
 #define	TCR_EL2_TG0_SHIFT	14
 #define	TCR_EL2_TG0_MASK	(0x3UL << TCR_EL2_TG0_SHIFT)
+#define	TCR_EL2_TG0_4K		(0x0UL << TCR_EL2_TG0_SHIFT)
+#define	TCR_EL2_TG0_64K		(0x1UL << TCR_EL2_TG0_SHIFT)
+#define	TCR_EL2_TG0_16K		(0x2UL << TCR_EL2_TG0_SHIFT)
 #define	TCR_EL2_PS_SHIFT	16
 #define	 TCR_EL2_PS_32BITS	(0UL << TCR_EL2_PS_SHIFT)
 #define	 TCR_EL2_PS_36BITS	(1UL << TCR_EL2_PS_SHIFT)
@@ -163,6 +174,18 @@
 #define	 TCR_EL2_PS_44BITS	(4UL << TCR_EL2_PS_SHIFT)
 #define	 TCR_EL2_PS_48BITS	(5UL << TCR_EL2_PS_SHIFT)
 #define	 TCR_EL2_PS_52BITS	(6UL << TCR_EL2_PS_SHIFT)
+#define	TCR_EL2_HPD_SHIFT	24
+#define	TCR_EL2_HPD		(1UL << TCR_EL2_HPD_SHIFT)
+#define	TCR_EL2_HWU59_SHIFT	25
+#define	TCR_EL2_HWU59		(1UL << TCR_EL2_HWU59_SHIFT)
+#define	TCR_EL2_HWU60_SHIFT	26
+#define	TCR_EL2_HWU60		(1UL << TCR_EL2_HWU60_SHIFT)
+#define	TCR_EL2_HWU61_SHIFT	27
+#define	TCR_EL2_HWU61		(1UL << TCR_EL2_HWU61_SHIFT)
+#define	TCR_EL2_HWU62_SHIFT	28
+#define	TCR_EL2_HWU62		(1UL << TCR_EL2_HWU62_SHIFT)
+#define	TCR_EL2_HWU		\
+    (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62)
 
 /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */
 #define	VMPIDR_EL2_U		0x0000000040000000
@@ -171,11 +194,16 @@
 
 /* VTCR_EL2 - Virtualization Translation Control Register */
 #define	VTCR_EL2_RES1		(0x1UL << 31)
-#define	VTCR_EL2_T0SZ_MASK	0x3f
+#define	VTCR_EL2_T0SZ_SHIFT	0
+#define	VTCR_EL2_T0SZ_MASK	(0x3fUL << VTCR_EL2_T0SZ_SHIFT)
+#define	VTCR_EL2_T0SZ(x)	((x) << VTCR_EL2_T0SZ_SHIFT)
 #define	VTCR_EL2_SL0_SHIFT	6
 #define	 VTCR_EL2_SL0_4K_LVL2	(0x0UL << VTCR_EL2_SL0_SHIFT)
 #define	 VTCR_EL2_SL0_4K_LVL1	(0x1UL << VTCR_EL2_SL0_SHIFT)
 #define	 VTCR_EL2_SL0_4K_LVL0	(0x2UL << VTCR_EL2_SL0_SHIFT)
+#define	 VTCR_EL2_SL0_16K_LVL2	(0x1UL << VTCR_EL2_SL0_SHIFT)
+#define	 VTCR_EL2_SL0_16K_LVL1	(0x2UL << VTCR_EL2_SL0_SHIFT)
+#define	 VTCR_EL2_SL0_16K_LVL0	(0x3UL << VTCR_EL2_SL0_SHIFT)
 #define	VTCR_EL2_IRGN0_SHIFT	8
 #define	 VTCR_EL2_IRGN0_WBWA	(0x1UL << VTCR_EL2_IRGN0_SHIFT)
 #define	VTCR_EL2_ORGN0_SHIFT	10