git: d5a64a935bc9 - stable/13 - Add initial DPAA2 support
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Date: Sun, 22 Jan 2023 14:09:14 UTC
The branch stable/13 has been updated by dsl:
URL: https://cgit.FreeBSD.org/src/commit/?id=d5a64a935bc92a89d61aafbb66acbf0e92980cb5
commit d5a64a935bc92a89d61aafbb66acbf0e92980cb5
Author: Dmitry Salychev <dsl@FreeBSD.org>
AuthorDate: 2022-09-20 09:47:41 +0000
Commit: Dmitry Salychev <dsl@FreeBSD.org>
CommitDate: 2023-01-22 14:06:23 +0000
Add initial DPAA2 support
DPAA2 is a hardware-level networking architecture found in some NXP
SoCs which contain hardware blocks including Management Complex
(MC, a command interface to manipulate DPAA2 objects), Wire Rate I/O
processor (WRIOP, packets distribution, queuing, drop decisions),
Queues and Buffers Manager (QBMan, Rx/Tx queues control, Rx buffer
pools) and the others.
The Management Complex runs NXP-supplied firmware which provides DPAA2
objects as an abstraction layer over those blocks to simplify an
access to the underlying hardware. Each DPAA2 object has its own
driver (to perform an initialization at least) and will be visible
as a separate device in the device tree.
Two new drivers (dpaa2_mc and dpaa2_rc) act like firmware buses in
order to form a hierarchy of the DPAA2 devices:
acpiX (or simplebusX)
dpaa2_mcX
dpaa2_rcX
dpaa2_mcp0
...
dpaa2_mcpN
dpaa2_bpX
dpaa2_macX
dpaa2_io0
...
dpaa2_ioM
dpaa2_niX
dpaa2_mc is suppossed to be a root of the hierarchy, comes in ACPI
and FDT flavours and implements helper interfaces to allocate and
assign bus resources, MSI and "managed" DPAA2 devices (NXP treats some
of the objects as resources for the other DPAA2 objects to let them
function properly). Almost all of the DPAA2 objects are assigned to
the resource containers (dpaa2_rc) to implement isolation.
The initial implementation focuses on the DPAA2 network interface
to be operational. It is the most complex object in terms of
dependencies which uses I/O objects to transmit/receive packets.
Approved by: bz (mentor)
Tested by: manu, bz
Differential Revision: https://reviews.freebsd.org/D36638
(cherry picked from commit ba7319e9091b4f6ef15a9c4be3d3d076f3047f72)
(cherry picked from commit 7fb975c8fb970b35fc34561ed30a0fe220346cb6)
(cherry picked from commit 2782ed8f6cd3d7f59219a783bc7fa7bbfb1fe26f)
(cherry picked from commit d6eabdac2ef444b62aba186c793fbd5d4226b157)
(cherry picked from commit 16295b0a5a577aa70f47d3b3314277e631caee63)
(cherry picked from commit ff270fce1631cdfbf8d3d76b9a9f5342b78972c9)
---
sys/arm64/conf/GENERIC | 1 +
sys/conf/files.arm64 | 19 +
sys/dev/dpaa2/dpaa2_bp.c | 205 +++
sys/dev/dpaa2/dpaa2_bp.h | 74 +
sys/dev/dpaa2/dpaa2_cmd_if.m | 1583 ++++++++++++++++
sys/dev/dpaa2/dpaa2_con.c | 213 +++
sys/dev/dpaa2/dpaa2_con.h | 70 +
sys/dev/dpaa2/dpaa2_io.c | 570 ++++++
sys/dev/dpaa2/dpaa2_io.h | 110 ++
sys/dev/dpaa2/dpaa2_mac.c | 376 ++++
sys/dev/dpaa2/dpaa2_mac.h | 124 ++
sys/dev/dpaa2/dpaa2_mc.c | 973 ++++++++++
sys/dev/dpaa2/dpaa2_mc.h | 218 +++
sys/dev/dpaa2/dpaa2_mc_acpi.c | 393 ++++
sys/dev/dpaa2/dpaa2_mc_fdt.c | 399 ++++
sys/dev/dpaa2/dpaa2_mc_if.m | 152 ++
sys/dev/dpaa2/dpaa2_mcp.c | 318 ++++
sys/dev/dpaa2/dpaa2_mcp.h | 449 +++++
sys/dev/dpaa2/dpaa2_ni.c | 3670 +++++++++++++++++++++++++++++++++++++
sys/dev/dpaa2/dpaa2_ni.h | 607 ++++++
sys/dev/dpaa2/dpaa2_ni_dpkg.h | 536 ++++++
sys/dev/dpaa2/dpaa2_rc.c | 3585 ++++++++++++++++++++++++++++++++++++
sys/dev/dpaa2/dpaa2_swp.c | 1169 ++++++++++++
sys/dev/dpaa2/dpaa2_swp.h | 504 +++++
sys/dev/dpaa2/dpaa2_swp_if.m | 96 +
sys/dev/dpaa2/dpaa2_types.h | 114 ++
sys/dev/dpaa2/memac_mdio.h | 64 +
sys/dev/dpaa2/memac_mdio_acpi.c | 310 ++++
sys/dev/dpaa2/memac_mdio_common.c | 306 ++++
sys/dev/dpaa2/memac_mdio_fdt.c | 308 ++++
sys/dev/dpaa2/memac_mdio_if.m | 42 +
sys/modules/Makefile | 2 +
sys/modules/dpaa2/Makefile | 42 +
33 files changed, 17602 insertions(+)
diff --git a/sys/arm64/conf/GENERIC b/sys/arm64/conf/GENERIC
index ceceb0e19c2e..9470c04646f0 100644
--- a/sys/arm64/conf/GENERIC
+++ b/sys/arm64/conf/GENERIC
@@ -286,6 +286,7 @@ device neta # Marvell Armada 370/38x/XP/3700 NIC
device re # RealTek 8139C+/8169/8169S/8110S
device smc # SMSC LAN91C111
device vnic # Cavium ThunderX NIC
+device dpaa2 # Data Path Acceleration Architecture (2nd Gen)
# Etherswitch devices
device etherswitch # Enable etherswitch support
diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index 8c60edc29448..a1f2fe03b24e 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -163,6 +163,25 @@ dev/axgbe/xgbe-phy-v1.c optional axa
dev/cpufreq/cpufreq_dt.c optional cpufreq fdt
+dev/dpaa2/dpaa2_bp.c optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_cmd_if.m optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_con.c optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_io.c optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_mac.c optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_mc.c optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_mc_acpi.c optional soc_nxp_ls dpaa2 acpi
+dev/dpaa2/dpaa2_mc_fdt.c optional soc_nxp_ls dpaa2 fdt
+dev/dpaa2/dpaa2_mc_if.m optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_mcp.c optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_ni.c optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_rc.c optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_swp.c optional soc_nxp_ls dpaa2
+dev/dpaa2/dpaa2_swp_if.m optional soc_nxp_ls dpaa2
+dev/dpaa2/memac_mdio_acpi.c optional soc_nxp_ls dpaa2 acpi
+dev/dpaa2/memac_mdio_common.c optional soc_nxp_ls dpaa2 acpi | soc_nxp_ls dpaa2 fdt
+dev/dpaa2/memac_mdio_fdt.c optional soc_nxp_ls dpaa2 fdt
+dev/dpaa2/memac_mdio_if.m optional soc_nxp_ls dpaa2 acpi | soc_nxp_ls dpaa2 fdt
+
dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 | fdt dwc_socfpga soc_intel_stratix10
dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 | fdt dwc_socfpga soc_intel_stratix10
diff --git a/sys/dev/dpaa2/dpaa2_bp.c b/sys/dev/dpaa2/dpaa2_bp.c
new file mode 100644
index 000000000000..78e1ca68cdb1
--- /dev/null
+++ b/sys/dev/dpaa2/dpaa2_bp.c
@@ -0,0 +1,205 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright © 2021-2022 Dmitry Salychev
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * The DPAA2 Buffer Pool (DPBP) driver.
+ *
+ * The DPBP configures a buffer pool that can be associated with DPAA2 network
+ * and accelerator interfaces.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+
+#include <vm/vm.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include "pcib_if.h"
+#include "pci_if.h"
+
+#include "dpaa2_mc.h"
+#include "dpaa2_mcp.h"
+#include "dpaa2_swp.h"
+#include "dpaa2_swp_if.h"
+#include "dpaa2_cmd_if.h"
+
+/* DPAA2 Buffer Pool resource specification. */
+struct resource_spec dpaa2_bp_spec[] = {
+ /*
+ * DPMCP resources.
+ *
+ * NOTE: MC command portals (MCPs) are used to send commands to, and
+ * receive responses from, the MC firmware. One portal per DPBP.
+ */
+#define MCP_RES_NUM (1u)
+#define MCP_RID_OFF (0u)
+#define MCP_RID(rid) ((rid) + MCP_RID_OFF)
+ /* --- */
+ { DPAA2_DEV_MCP, MCP_RID(0), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
+ /* --- */
+ RESOURCE_SPEC_END
+};
+
+static int
+dpaa2_bp_probe(device_t dev)
+{
+ /* DPBP device will be added by the parent resource container. */
+ device_set_desc(dev, "DPAA2 Buffer Pool");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+dpaa2_bp_detach(device_t dev)
+{
+ device_t child = dev;
+ struct dpaa2_bp_softc *sc = device_get_softc(dev);
+ struct dpaa2_devinfo *dinfo = device_get_ivars(dev);
+
+ if (sc->cmd != NULL) {
+ (void)DPAA2_CMD_BP_DISABLE(dev, child, sc->cmd);
+ (void)DPAA2_CMD_BP_CLOSE(dev, child, dpaa2_mcp_tk(sc->cmd,
+ sc->bp_token));
+ (void)DPAA2_CMD_RC_CLOSE(dev, child, dpaa2_mcp_tk(sc->cmd,
+ sc->rc_token));
+
+ dpaa2_mcp_free_command(sc->cmd);
+ sc->cmd = NULL;
+ }
+
+ dinfo->portal = NULL;
+ bus_release_resources(sc->dev, dpaa2_bp_spec, sc->res);
+
+ return (0);
+}
+
+static int
+dpaa2_bp_attach(device_t dev)
+{
+ device_t pdev = device_get_parent(dev);
+ device_t child = dev;
+ device_t mcp_dev;
+ struct dpaa2_bp_softc *sc = device_get_softc(dev);
+ struct dpaa2_devinfo *rcinfo = device_get_ivars(pdev);
+ struct dpaa2_devinfo *dinfo = device_get_ivars(dev);
+ struct dpaa2_devinfo *mcp_dinfo;
+ int error;
+
+ sc->dev = dev;
+ sc->cmd = NULL;
+
+ error = bus_alloc_resources(sc->dev, dpaa2_bp_spec, sc->res);
+ if (error) {
+ device_printf(dev, "%s: failed to allocate resources: "
+ "error=%d\n", __func__, error);
+ return (ENXIO);
+ }
+
+ /* Send commands to MC via allocated portal. */
+ mcp_dev = (device_t) rman_get_start(sc->res[MCP_RID(0)]);
+ mcp_dinfo = device_get_ivars(mcp_dev);
+ dinfo->portal = mcp_dinfo->portal;
+
+ /* Allocate a command to send to MC hardware. */
+ error = dpaa2_mcp_init_command(&sc->cmd, DPAA2_CMD_DEF);
+ if (error) {
+ device_printf(dev, "%s: failed to allocate dpaa2_cmd: "
+ "error=%d\n", __func__, error);
+ dpaa2_bp_detach(dev);
+ return (ENXIO);
+ }
+
+ /* Open resource container and DPBP object. */
+ error = DPAA2_CMD_RC_OPEN(dev, child, sc->cmd, rcinfo->id,
+ &sc->rc_token);
+ if (error) {
+ device_printf(dev, "%s: failed to open DPRC: error=%d\n",
+ __func__, error);
+ dpaa2_bp_detach(dev);
+ return (ENXIO);
+ }
+ error = DPAA2_CMD_BP_OPEN(dev, child, sc->cmd, dinfo->id, &sc->bp_token);
+ if (error) {
+ device_printf(dev, "%s: failed to open DPBP: id=%d, error=%d\n",
+ __func__, dinfo->id, error);
+ dpaa2_bp_detach(dev);
+ return (ENXIO);
+ }
+
+ /* Prepare DPBP object. */
+ error = DPAA2_CMD_BP_RESET(dev, child, sc->cmd);
+ if (error) {
+ device_printf(dev, "%s: failed to reset DPBP: id=%d, error=%d\n",
+ __func__, dinfo->id, error);
+ dpaa2_bp_detach(dev);
+ return (ENXIO);
+ }
+ error = DPAA2_CMD_BP_ENABLE(dev, child, sc->cmd);
+ if (error) {
+ device_printf(dev, "%s: failed to enable DPBP: id=%d, "
+ "error=%d\n", __func__, dinfo->id, error);
+ dpaa2_bp_detach(dev);
+ return (ENXIO);
+ }
+ error = DPAA2_CMD_BP_GET_ATTRIBUTES(dev, child, sc->cmd, &sc->attr);
+ if (error) {
+ device_printf(dev, "%s: failed to get DPBP attributes: id=%d, "
+ "error=%d\n", __func__, dinfo->id, error);
+ dpaa2_bp_detach(dev);
+ return (ENXIO);
+ }
+
+ return (0);
+}
+
+static device_method_t dpaa2_bp_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, dpaa2_bp_probe),
+ DEVMETHOD(device_attach, dpaa2_bp_attach),
+ DEVMETHOD(device_detach, dpaa2_bp_detach),
+
+ DEVMETHOD_END
+};
+
+static driver_t dpaa2_bp_driver = {
+ "dpaa2_bp",
+ dpaa2_bp_methods,
+ sizeof(struct dpaa2_bp_softc),
+};
+
+DRIVER_MODULE(dpaa2_bp, dpaa2_rc, dpaa2_bp_driver, 0, 0);
diff --git a/sys/dev/dpaa2/dpaa2_bp.h b/sys/dev/dpaa2/dpaa2_bp.h
new file mode 100644
index 000000000000..3ba7196eb030
--- /dev/null
+++ b/sys/dev/dpaa2/dpaa2_bp.h
@@ -0,0 +1,74 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright © 2022 Dmitry Salychev
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _DPAA2_BP_H
+#define _DPAA2_BP_H
+
+#include <sys/bus.h>
+
+/* Maximum resources per DPBP: 1 DPMCP. */
+#define DPAA2_BP_MAX_RESOURCES 1
+
+/**
+ * @brief Attributes of the DPBP object.
+ *
+ * id: DPBP object ID.
+ * bpid: Hardware buffer pool ID; should be used as an argument in
+ * acquire/release operations on buffers.
+ */
+struct dpaa2_bp_attr {
+ uint32_t id;
+ uint16_t bpid;
+};
+
+/**
+ * @brief Configuration/state of the buffer pool.
+ */
+struct dpaa2_bp_conf {
+ uint8_t bdi;
+ uint8_t state; /* bitmask */
+ uint32_t free_bufn;
+};
+
+/**
+ * @brief Software context for the DPAA2 Buffer Pool driver.
+ */
+struct dpaa2_bp_softc {
+ device_t dev;
+ struct dpaa2_bp_attr attr;
+
+ /* Help to send commands to MC. */
+ struct dpaa2_cmd *cmd;
+ uint16_t rc_token;
+ uint16_t bp_token;
+
+ struct resource *res[DPAA2_BP_MAX_RESOURCES];
+};
+
+extern struct resource_spec dpaa2_bp_spec[];
+
+#endif /* _DPAA2_BP_H */
diff --git a/sys/dev/dpaa2/dpaa2_cmd_if.m b/sys/dev/dpaa2/dpaa2_cmd_if.m
new file mode 100644
index 000000000000..96031d4ae8c5
--- /dev/null
+++ b/sys/dev/dpaa2/dpaa2_cmd_if.m
@@ -0,0 +1,1583 @@
+#-
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright © 2021-2022 Dmitry Salychev
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+# SUCH DAMAGE.
+#
+
+#include <machine/bus.h>
+#include <dev/dpaa2/dpaa2_types.h>
+#include <dev/dpaa2/dpaa2_mc.h>
+#include <dev/dpaa2/dpaa2_mcp.h>
+
+/**
+ * @brief DPAA2 MC command interface.
+ *
+ * The primary purpose of the MC provided DPAA2 objects is to simplify DPAA2
+ * hardware block usage through abstraction and encapsulation.
+ */
+INTERFACE dpaa2_cmd;
+
+#
+# Default implementation of the commands.
+#
+CODE {
+ static void
+ panic_on_mc(device_t dev)
+ {
+ if (strcmp(device_get_name(dev), "dpaa2_mc") == 0)
+ panic("No one can handle a command above DPAA2 MC");
+ }
+
+ static int
+ bypass_mng_get_version(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint32_t *major, uint32_t *minor, uint32_t *rev)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_MNG_GET_VERSION(device_get_parent(dev), child,
+ cmd, major, minor, rev));
+ return (ENXIO);
+ }
+ static int
+ bypass_mng_get_soc_version(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint32_t *pvr, uint32_t *svr)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_MNG_GET_SOC_VERSION(
+ device_get_parent(dev), child, cmd, pvr, svr));
+ return (ENXIO);
+ }
+ static int
+ bypass_mng_get_container_id(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint32_t *cont_id)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_MNG_GET_CONTAINER_ID(
+ device_get_parent(dev), child, cmd, cont_id));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_open(device_t dev, device_t child, struct dpaa2_cmd *cmd, uint32_t cont_id,
+ uint16_t *token)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_OPEN(
+ device_get_parent(dev), child, cmd, cont_id, token));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_close(device_t dev, device_t child, struct dpaa2_cmd *cmd)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_CLOSE(
+ device_get_parent(dev), child, cmd));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_get_obj_count(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint32_t *obj_count)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_GET_OBJ_COUNT(
+ device_get_parent(dev), child, cmd, obj_count));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_get_obj(device_t dev, device_t child, struct dpaa2_cmd *cmd, uint32_t obj_idx,
+ struct dpaa2_obj *obj)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_GET_OBJ(
+ device_get_parent(dev), child, cmd, obj_idx, obj));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_get_obj_descriptor(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint32_t obj_id, enum dpaa2_dev_type type, struct dpaa2_obj *obj)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_GET_OBJ_DESCRIPTOR(
+ device_get_parent(dev), child, cmd, obj_id, type, obj));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_get_attributes(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_rc_attr *attr)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_GET_ATTRIBUTES(
+ device_get_parent(dev), child, cmd, attr));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_get_obj_region(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint32_t obj_id, uint8_t reg_idx, enum dpaa2_dev_type type,
+ struct dpaa2_rc_obj_region *reg)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_GET_OBJ_REGION(
+ device_get_parent(dev), child, cmd, obj_id, reg_idx,
+ type, reg));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_get_api_version(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint16_t *major, uint16_t *minor)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_GET_API_VERSION(
+ device_get_parent(dev), child, cmd, major, minor));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_set_irq_enable(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t irq_idx, uint8_t enable)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_SET_IRQ_ENABLE(
+ device_get_parent(dev), child, cmd, irq_idx, enable));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_set_obj_irq(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t irq_idx, uint64_t addr, uint32_t data, uint32_t irq_usr,
+ uint32_t obj_id, enum dpaa2_dev_type type)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_SET_OBJ_IRQ(
+ device_get_parent(dev), child, cmd, irq_idx, addr, data,
+ irq_usr, obj_id, type));
+ return (ENXIO);
+ }
+ static int
+ bypass_rc_get_conn(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ep_desc *ep1_desc, struct dpaa2_ep_desc *ep2_desc,
+ uint32_t *link_stat)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_RC_GET_CONN(
+ device_get_parent(dev), child, cmd, ep1_desc, ep2_desc,
+ link_stat));
+ return (ENXIO);
+ }
+
+ static int
+ bypass_ni_open(device_t dev, device_t child, struct dpaa2_cmd *cmd, uint32_t dpni_id,
+ uint16_t *token)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_OPEN(
+ device_get_parent(dev), child, cmd, dpni_id, token));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_close(device_t dev, device_t child, struct dpaa2_cmd *cmd)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_CLOSE(
+ device_get_parent(dev), child, cmd));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_enable(device_t dev, device_t child, struct dpaa2_cmd *cmd)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_ENABLE(
+ device_get_parent(dev), child, cmd));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_disable(device_t dev, device_t child, struct dpaa2_cmd *cmd)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_DISABLE(
+ device_get_parent(dev), child, cmd));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_api_version(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint16_t *major, uint16_t *minor)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_API_VERSION(
+ device_get_parent(dev), child, cmd, major, minor));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_reset(device_t dev, device_t child, struct dpaa2_cmd *cmd)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_RESET(
+ device_get_parent(dev), child, cmd));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_attributes(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_attr *attr)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_ATTRIBUTES(
+ device_get_parent(dev), child, cmd, attr));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_buf_layout(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_buf_layout *bl)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_BUF_LAYOUT(
+ device_get_parent(dev), child, cmd, bl));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_tx_data_off(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint16_t *offset)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_TX_DATA_OFF(
+ device_get_parent(dev), child, cmd, offset));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_link_cfg(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_link_cfg *cfg)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_LINK_CFG(
+ device_get_parent(dev), child, cmd, cfg));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_link_cfg(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_link_cfg *cfg)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_LINK_CFG(
+ device_get_parent(dev), child, cmd, cfg));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_link_state(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_link_state *state)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_LINK_STATE(
+ device_get_parent(dev), child, cmd, state));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_port_mac_addr(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t *mac)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_PORT_MAC_ADDR(
+ device_get_parent(dev), child, cmd, mac));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_prim_mac_addr(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t *mac)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_PRIM_MAC_ADDR(
+ device_get_parent(dev), child, cmd, mac));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_prim_mac_addr(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t *mac)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_PRIM_MAC_ADDR(
+ device_get_parent(dev), child, cmd, mac));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_qos_table(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_qos_table *tbl)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_QOS_TABLE(
+ device_get_parent(dev), child, cmd, tbl));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_clear_qos_table(device_t dev, device_t child, struct dpaa2_cmd *cmd)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_CLEAR_QOS_TABLE(
+ device_get_parent(dev), child, cmd));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_pools(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_pools_cfg *cfg)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_POOLS(
+ device_get_parent(dev), child, cmd, cfg));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_err_behavior(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_err_cfg *cfg)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_ERR_BEHAVIOR(
+ device_get_parent(dev), child, cmd, cfg));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_queue(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_queue_cfg *cfg)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_QUEUE(
+ device_get_parent(dev), child, cmd, cfg));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_queue(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ struct dpaa2_ni_queue_cfg *cfg)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_QUEUE(
+ device_get_parent(dev), child, cmd, cfg));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_qdid(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ enum dpaa2_ni_queue_type type, uint16_t *qdid)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_QDID(
+ device_get_parent(dev), child, cmd, type, qdid));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_add_mac_addr(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t *mac)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_ADD_MAC_ADDR(
+ device_get_parent(dev), child, cmd, mac));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_remove_mac_addr(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t *mac)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_REMOVE_MAC_ADDR(
+ device_get_parent(dev), child, cmd, mac));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_clear_mac_filters(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ bool rm_uni, bool rm_multi)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_CLEAR_MAC_FILTERS(
+ device_get_parent(dev), child, cmd, rm_uni, rm_multi));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_mfl(device_t dev, device_t child, struct dpaa2_cmd *cmd, uint16_t length)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_MFL(
+ device_get_parent(dev), child, cmd, length));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_offload(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ enum dpaa2_ni_ofl_type ofl_type, bool en)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_OFFLOAD(
+ device_get_parent(dev), child, cmd, ofl_type, en));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_irq_mask(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t irq_idx, uint32_t mask)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_IRQ_MASK(
+ device_get_parent(dev), child, cmd, irq_idx, mask));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_irq_enable(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t irq_idx, bool en)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_IRQ_ENABLE(
+ device_get_parent(dev), child, cmd, irq_idx, en));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_irq_status(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t irq_idx, uint32_t *status)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_IRQ_STATUS(
+ device_get_parent(dev), child, cmd, irq_idx, status));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_uni_promisc(device_t dev, device_t child, struct dpaa2_cmd *cmd, bool en)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_UNI_PROMISC(
+ device_get_parent(dev), child, cmd, en));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_multi_promisc(device_t dev, device_t child, struct dpaa2_cmd *cmd, bool en)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_MULTI_PROMISC(
+ device_get_parent(dev), child, cmd, en));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_get_statistics(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint8_t page, uint16_t param, uint64_t *cnt)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_GET_STATISTICS(
+ device_get_parent(dev), child, cmd, page, param, cnt));
+ return (ENXIO);
+ }
+ static int
+ bypass_ni_set_rx_tc_dist(device_t dev, device_t child, struct dpaa2_cmd *cmd,
+ uint16_t dist_size, uint8_t tc, enum dpaa2_ni_dist_mode dist_mode,
+ bus_addr_t key_cfg_buf)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_NI_SET_RX_TC_DIST(
+ device_get_parent(dev), child, cmd, dist_size, tc,
+ dist_mode, key_cfg_buf));
+ return (ENXIO);
+ }
+
+ static int
+ bypass_io_open(device_t dev, device_t child, struct dpaa2_cmd *cmd, uint32_t dpio_id,
+ uint16_t *token)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_IO_OPEN(
+ device_get_parent(dev), child, cmd, dpio_id, token));
+ return (ENXIO);
+ }
+ static int
+ bypass_io_close(device_t dev, device_t child, struct dpaa2_cmd *cmd)
+ {
+ panic_on_mc(dev);
+ if (device_get_parent(dev) != NULL)
+ return (DPAA2_CMD_IO_CLOSE(
+ device_get_parent(dev), child, cmd));
+ return (ENXIO);
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