git: df7798be4e38 - stable/13 - pci: add tunable hw.pci.enable_mps_tune

From: Corvin Köhne <>
Date: Wed, 05 Apr 2023 08:08:43 UTC
The branch stable/13 has been updated by corvink:


commit df7798be4e388fe6d40184021c8885f5d43b769b
Author:     Corvin Köhne <>
AuthorDate: 2023-02-06 09:26:33 +0000
Commit:     Corvin Köhne <>
CommitDate: 2023-04-05 07:15:26 +0000

    pci: add tunable hw.pci.enable_mps_tune
    If the tunable is set to 0, the tuning of the MPS (maximum payload size)
    is disabled and the default MPS values set by the BIOS are used. In this
    case the system may use a lower speed or operate in a less optimized
    state, but it can resolve issues with stability and compatibility. With
    specific devices the tuning of the mps, can lead to a complete freeze of
    the system.
    Reviewed by:            manu
    MFC after:              1 week
    Sponsored by:           Beckhoff Automation GmbH & Co. KG
    Differential Revision:
    (cherry picked from commit 48d70503bcae816eea6109c30ba79261eb47c9d0)
 sys/dev/pci/pci.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c
index 97f6f4da1821..b38311e41d84 100644
--- a/sys/dev/pci/pci.c
+++ b/sys/dev/pci/pci.c
@@ -421,6 +421,11 @@ SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN,
     &pci_clear_aer_on_attach, 0,
     "Clear port and device AER state on driver attach");
+static bool pci_enable_mps_tune = true;
+SYSCTL_BOOL(_hw_pci, OID_AUTO, enable_mps_tune, CTLFLAG_RWTUN,
+    &pci_enable_mps_tune, 1,
+    "Enable tuning of MPS(maximum payload size)." );
 static int
 pci_has_quirk(uint32_t devid, int quirk)
@@ -4453,7 +4458,8 @@ pci_add_child(device_t bus, struct pci_devinfo *dinfo)
 	pci_cfg_restore(dev, dinfo);
 	pci_add_resources(bus, dev, 0, 0);
-	pcie_setup_mps(dev);
+	if (pci_enable_mps_tune)
+		pcie_setup_mps(dev);
 	if (pci_clear_aer_on_attach)