git: a0290386cf0d - stable/13 - Add support for arm64 nGnRE device memory

The branch stable/13 has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=a0290386cf0de2b3e9e36df9cd37f213b59ca628

commit a0290386cf0de2b3e9e36df9cd37f213b59ca628
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2021-02-05 10:50:29 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2022-04-19 09:17:57 +0000

    Add support for arm64 nGnRE device memory
    
    On arm64 we can select how strongly we order device memory. Currently
    we use the strongest type of non-Gathering, non-Reordering, no Early
    write acknowledgement. This is equivalent to VM_MEMATTR_SO in the 32-bit
    arm code.
    
    Create a new memory type to remove the no Early write acknowledgement
    option to create a memory attribute that is equivalent to the arm
    VM_MEMATTR_DEVICE.
    
    Keep the the old nGnRnE memory as what we provide for VM_MEMATTR_DEVICE
    until we can test nGnRE on more hardware. A method for dynamically
    switching back may be needed as at least one vendor is known to have
    broken nGnRE memory.
    
    Sponsored by:   Innovate UK
    
    (cherry picked from commit 13ec5a6da04b14c4d40d3b37335dfaef7469aeb5)
---
 sys/arm64/arm64/locore.S   | 5 +++--
 sys/arm64/include/armreg.h | 1 +
 sys/arm64/include/vm.h     | 5 ++++-
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index 37483c321f48..cbc84a0efd52 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -748,10 +748,11 @@ LENTRY(start_mmu)
 
 	.align 3
 mair:
-	.quad	MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE)    |	\
+	.quad	MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \
 		MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE)   |	\
 		MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK)    |	\
-		MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH)
+		MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) |	\
+		MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE)
 tcr:
 	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | TCR_TG0_4K | \
 	    TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index dcaab1375bf8..1b46d0833429 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1123,6 +1123,7 @@
 #define	MAIR_ATTR_MASK(idx)	(0xff << ((n)* 8))
 #define	MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
 #define	 MAIR_DEVICE_nGnRnE	0x00
+#define	 MAIR_DEVICE_nGnRE	0x04
 #define	 MAIR_NORMAL_NC		0x44
 #define	 MAIR_NORMAL_WT		0xbb
 #define	 MAIR_NORMAL_WB		0xff
diff --git a/sys/arm64/include/vm.h b/sys/arm64/include/vm.h
index dac13980060e..3df3af24c010 100644
--- a/sys/arm64/include/vm.h
+++ b/sys/arm64/include/vm.h
@@ -30,10 +30,13 @@
 #define	_MACHINE_VM_H_
 
 /* Memory attribute configuration. */
-#define	VM_MEMATTR_DEVICE		0
+#define	VM_MEMATTR_DEVICE_nGnRnE	0
 #define	VM_MEMATTR_UNCACHEABLE		1
 #define	VM_MEMATTR_WRITE_BACK		2
 #define	VM_MEMATTR_WRITE_THROUGH	3
+#define	VM_MEMATTR_DEVICE_nGnRE		4
+
+#define	VM_MEMATTR_DEVICE		VM_MEMATTR_DEVICE_nGnRnE
 
 #ifdef _KERNEL
 /* If defined vmstat will try to use both of these in a switch statement */