From nobody Mon Nov 22 18:22:44 2021 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 2510C18A2442; Mon, 22 Nov 2021 18:22:45 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4HybGr4kRpz3Lbl; Mon, 22 Nov 2021 18:22:44 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 8248427754; Mon, 22 Nov 2021 18:22:44 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 1AMIMioC011810; Mon, 22 Nov 2021 18:22:44 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 1AMIMiYn011809; Mon, 22 Nov 2021 18:22:44 GMT (envelope-from git) Date: Mon, 22 Nov 2021 18:22:44 GMT Message-Id: <202111221822.1AMIMiYn011809@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Allan Jude Subject: git: 0ed191d116f5 - stable/12 - openssl: Fix detection of ARMv7 and ARM64 CPU features List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: allanjude X-Git-Repository: src X-Git-Refname: refs/heads/stable/12 X-Git-Reftype: branch X-Git-Commit: 0ed191d116f511c1e67338f05386d87aad53076f Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch stable/12 has been updated by allanjude: URL: https://cgit.FreeBSD.org/src/commit/?id=0ed191d116f511c1e67338f05386d87aad53076f commit 0ed191d116f511c1e67338f05386d87aad53076f Author: Allan Jude AuthorDate: 2021-11-19 15:14:30 +0000 Commit: Allan Jude CommitDate: 2021-11-22 18:22:36 +0000 openssl: Fix detection of ARMv7 and ARM64 CPU features OpenSSL assumes the same value for AT_HWCAP=16 (Linux) So it ends up calling elf_auxv_info() with AT_CANARY which returns ENOENT, and all acceleration features are disabled. With this, my ARM64 test machine runs the benchmark `openssl speed -evp aes-256-gcm` nearly 20x faster going from 100 MB/sec to 2000 MB/sec It also improves sha256 from 300 MB/sec to 1800 MB/sec This fix has been accepted but not yet merged upstream: https://github.com/openssl/openssl/pull/17082 PR: 259937 Reviewed by: manu, imp MFC after: immediate Relnotes: yes Fixes: 88e852c0b5c872b1a ("OpenSSL: Merge OpenSSL 1.1.1j") Sponsored by: Ampere Computing LLC Sponsored by: Klara Inc. Differential Revision: https://reviews.freebsd.org/D33060 (cherry picked from commit d9bb798725cfce9c72b80440659b48e8668eb10d) --- crypto/openssl/crypto/armcap.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/crypto/openssl/crypto/armcap.c b/crypto/openssl/crypto/armcap.c index c5685bde5891..48c5d4d64e32 100644 --- a/crypto/openssl/crypto/armcap.c +++ b/crypto/openssl/crypto/armcap.c @@ -106,20 +106,23 @@ static unsigned long getauxval(unsigned long key) * ARM puts the feature bits for Crypto Extensions in AT_HWCAP2, whereas * AArch64 used AT_HWCAP. */ +# ifndef AT_HWCAP +# define AT_HWCAP 16 +# endif +# ifndef AT_HWCAP2 +# define AT_HWCAP2 26 +# endif # if defined(__arm__) || defined (__arm) -# define HWCAP 16 - /* AT_HWCAP */ +# define HWCAP AT_HWCAP # define HWCAP_NEON (1 << 12) -# define HWCAP_CE 26 - /* AT_HWCAP2 */ +# define HWCAP_CE AT_HWCAP2 # define HWCAP_CE_AES (1 << 0) # define HWCAP_CE_PMULL (1 << 1) # define HWCAP_CE_SHA1 (1 << 2) # define HWCAP_CE_SHA256 (1 << 3) # elif defined(__aarch64__) -# define HWCAP 16 - /* AT_HWCAP */ +# define HWCAP AT_HWCAP # define HWCAP_NEON (1 << 1) # define HWCAP_CE HWCAP