From nobody Thu Sep 24 12:51:10 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4hrDGl1ggFz6sM3X for ; Thu, 24 Sep 2026 12:51:11 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4hrDGl11MWz4rHM for ; Thu, 24 Sep 2026 12:51:11 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1790254271; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=dW96lZkqitXnHIQc6j8YJQ3gaRmBtYvssh6+1qyh3+8=; b=goRaLrtAfo0FvZkGqkyoxFBpkqI6f9v4cNcFqch1ERVgMkr5sNcML6ukcliv/nDgynr/lD N9C5tNGQIFMas8uNriH8lvWjs/XbLecxzb0fhkzzhntuTDwmMeA9lkmW21CxdJFKd9DRIo a2Z2AevUkQ2EN6qE3nKDY9MkbtoLBtNEb8y3z/2eePKFko0JbkGtZh0PNsc74afWyqHzc8 M3yzCDgOAnYZmFCCRPCXxlYPobJBi1r0DOVVUUacbdt9gHsDEgFhgjZUkEdYAQGEr5Qa1M qeGIquZoeebiLb4ZqD/83/Th1p5Avb6fp0mcJbVMd7qd2/HnpvAezPBcfNMDmw== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1790254271; b=cbNvj/SCPUmflSjr1CQX2ljCFxNjWCHcth8BvUwEY0oLBFSxfQjbVHkv0/FPT4K7KWQfxq gyh/2ILNNE7SIbhyW2kaluuCztZhQ9VNxinB6OTaLFeKpbGPj/8BRUFF9RGNtLgs9vgDpK H+j4NgKyxyx1nJ94MNzLORJhZI/xDIuwg87qhSsXYuGWs+jkxFisXgVdB5ScM1KknSjLkv sFaFHyAlrKC7aa/AxcIFJEZQIGajbLz0XHYNCMSQ8ImPLmyHKbQ/vsbhLyyv20kGs5jmki a2s1Dqf9s85ynRPyeKS/9qWNOYebSJHLZyfR63tSGgAzVNL6aFZN+3aHNdyvXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1790254271; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=dW96lZkqitXnHIQc6j8YJQ3gaRmBtYvssh6+1qyh3+8=; b=f/YezzUuZs9mXyIVCNwEhg+pxdvn5mhZZaK7dnLZ4cr+8MzR9DnxbE9cztEpbRz2MzKK+a KbHiJfMrOiz4nJZKK5yz6r2+jWW7DqRN6nkukohRVFbPMeikmjpu6qYCKw/nRfoAsTrZz+ amwivP05oKgJHauzk5ksxxZl3604Rac4uGrNknQgxfdz5dUObBpUNniDs7fOyZu/a2i1oa A/pBOuAD2SvDqZoY74NiakKScOIa+x5rbb+Xy62Z0Mb8MUc2sjREOa0LO49TUummK/yX8k lKuwh7MOR6ZKVLWum84OTmFyaUTog53UyFqYpovy/bEDtS7itiJeXQV/hdbn2g== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4hrDGl03snzNy8 for ; Thu, 24 Sep 2026 12:51:11 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 26bb6 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Thu, 24 Sep 2026 12:51:10 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Dimitry Andric Subject: git: b5d1e0c5a492 - main - llvm: remove Mips target support List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: dim X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: b5d1e0c5a4929e2be3bc58aad8e5b707860ec0fd Auto-Submitted: auto-generated Date: Thu, 24 Sep 2026 12:51:10 +0000 Message-Id: <6ab51cbe.26bb6.2734fed2@gitrepo.freebsd.org> The branch main has been updated by dim: URL: https://cgit.FreeBSD.org/src/commit/?id=b5d1e0c5a4929e2be3bc58aad8e5b707860ec0fd commit b5d1e0c5a4929e2be3bc58aad8e5b707860ec0fd Author: Dimitry Andric AuthorDate: 2026-09-24 12:50:47 +0000 Commit: Dimitry Andric CommitDate: 2026-09-24 12:50:47 +0000 llvm: remove Mips target support The Mips architecture has been removed from all supported branches now. MFC after: 1 week --- lib/clang/include/llvm/Config/AsmParsers.def | 3 - lib/clang/include/llvm/Config/AsmPrinters.def | 3 - lib/clang/include/llvm/Config/Disassemblers.def | 3 - lib/clang/include/llvm/Config/Targets.def | 3 - lib/clang/include/llvm/Config/Targets.h | 4 -- lib/clang/libllvm/Makefile | 89 ++----------------------- lib/clang/llvm.build.mk | 3 - share/man/man5/src.conf.5 | 7 +- share/mk/src.opts.mk | 2 +- tools/build/options/WITHOUT_LLVM_TARGET_MIPS | 4 -- tools/build/options/WITH_LLVM_TARGET_MIPS | 4 -- 11 files changed, 8 insertions(+), 117 deletions(-) diff --git a/lib/clang/include/llvm/Config/AsmParsers.def b/lib/clang/include/llvm/Config/AsmParsers.def index 3dccab75a285..8cf3ffd6b0d4 100644 --- a/lib/clang/include/llvm/Config/AsmParsers.def +++ b/lib/clang/include/llvm/Config/AsmParsers.def @@ -33,9 +33,6 @@ LLVM_ASM_PARSER(ARM) #ifdef LLVM_TARGET_ENABLE_BPF LLVM_ASM_PARSER(BPF) #endif -#ifdef LLVM_TARGET_ENABLE_MIPS -LLVM_ASM_PARSER(Mips) -#endif #ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_ASM_PARSER(PowerPC) #endif diff --git a/lib/clang/include/llvm/Config/AsmPrinters.def b/lib/clang/include/llvm/Config/AsmPrinters.def index 649b8353c926..b88e60ada874 100644 --- a/lib/clang/include/llvm/Config/AsmPrinters.def +++ b/lib/clang/include/llvm/Config/AsmPrinters.def @@ -33,9 +33,6 @@ LLVM_ASM_PRINTER(ARM) #ifdef LLVM_TARGET_ENABLE_BPF LLVM_ASM_PRINTER(BPF) #endif -#ifdef LLVM_TARGET_ENABLE_MIPS -LLVM_ASM_PRINTER(Mips) -#endif #ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_ASM_PRINTER(PowerPC) #endif diff --git a/lib/clang/include/llvm/Config/Disassemblers.def b/lib/clang/include/llvm/Config/Disassemblers.def index c44fa4e303e2..72c0dcab0ab3 100644 --- a/lib/clang/include/llvm/Config/Disassemblers.def +++ b/lib/clang/include/llvm/Config/Disassemblers.def @@ -33,9 +33,6 @@ LLVM_DISASSEMBLER(ARM) #ifdef LLVM_TARGET_ENABLE_BPF LLVM_DISASSEMBLER(BPF) #endif -#ifdef LLVM_TARGET_ENABLE_MIPS -LLVM_DISASSEMBLER(Mips) -#endif #ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_DISASSEMBLER(PowerPC) #endif diff --git a/lib/clang/include/llvm/Config/Targets.def b/lib/clang/include/llvm/Config/Targets.def index d3332a51a2cc..725efe253ced 100644 --- a/lib/clang/include/llvm/Config/Targets.def +++ b/lib/clang/include/llvm/Config/Targets.def @@ -32,9 +32,6 @@ LLVM_TARGET(ARM) #ifdef LLVM_TARGET_ENABLE_BPF LLVM_TARGET(BPF) #endif -#ifdef LLVM_TARGET_ENABLE_MIPS -LLVM_TARGET(Mips) -#endif #ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_TARGET(PowerPC) #endif diff --git a/lib/clang/include/llvm/Config/Targets.h b/lib/clang/include/llvm/Config/Targets.h index ce9bffebe10f..ccb524e96fa2 100644 --- a/lib/clang/include/llvm/Config/Targets.h +++ b/lib/clang/include/llvm/Config/Targets.h @@ -61,11 +61,7 @@ #define LLVM_HAS_M68K_TARGET 0 /* Define if the Mips target is built in */ -#ifdef LLVM_TARGET_ENABLE_MIPS -#define LLVM_HAS_MIPS_TARGET 1 -#else #define LLVM_HAS_MIPS_TARGET 0 -#endif /* Define if the MSP430 target is built in */ #define LLVM_HAS_MSP430_TARGET 0 diff --git a/lib/clang/libllvm/Makefile b/lib/clang/libllvm/Makefile index a234c73b15b9..9baa95c19242 100644 --- a/lib/clang/libllvm/Makefile +++ b/lib/clang/libllvm/Makefile @@ -27,15 +27,14 @@ CFLAGS+= -I${.OBJDIR} CFLAGS+= -I${SRCTOP}/sys/contrib/zstd/lib .if ${MK_LLVM_TARGET_AARCH64} == "no" && ${MK_LLVM_TARGET_ARM} == "no" && \ - ${MK_LLVM_TARGET_BPF} == "no" && ${MK_LLVM_TARGET_MIPS} == "no" && \ - ${MK_LLVM_TARGET_POWERPC} == "no" && ${MK_LLVM_TARGET_RISCV} == "no" && \ - ${MK_LLVM_TARGET_X86} == "no" + ${MK_LLVM_TARGET_BPF} == "no" && ${MK_LLVM_TARGET_POWERPC} == "no" && \ + ${MK_LLVM_TARGET_RISCV} == "no" && ${MK_LLVM_TARGET_X86} == "no" .error Please enable at least one of: MK_LLVM_TARGET_AARCH64,\ - MK_LLVM_TARGET_ARM, MK_LLVM_TARGET_BPF, MK_LLVM_TARGET_MIPS, \ - MK_LLVM_TARGET_POWERPC, MK_LLVM_TARGET_RISCV, or MK_LLVM_TARGET_X86 + MK_LLVM_TARGET_ARM, MK_LLVM_TARGET_BPF, MK_LLVM_TARGET_POWERPC,\ + MK_LLVM_TARGET_RISCV, or MK_LLVM_TARGET_X86 .endif -.for arch in AArch64 ARM BPF Mips PowerPC RISCV X86 +.for arch in AArch64 ARM BPF PowerPC RISCV X86 . if ${MK_LLVM_TARGET_${arch:tu}} != "no" CFLAGS+= -I${LLVM_SRCS}/lib/Target/${arch} . endif @@ -1544,65 +1543,6 @@ SRCS_MIN+= Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp SRCS_MIN+= Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp SRCS_MIN+= Target/BPF/TargetInfo/BPFTargetInfo.cpp .endif # MK_LLVM_TARGET_BPF -.if ${MK_LLVM_TARGET_MIPS} != "no" -SRCS_MIN+= Target/Mips/AsmParser/MipsAsmParser.cpp -SRCS_XDW+= Target/Mips/Disassembler/MipsDisassembler.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsABIInfo.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsAsmBackend.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsELFStreamer.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsInstPrinter.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsOptionRecord.cpp -SRCS_MIN+= Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp -SRCS_MIN+= Target/Mips/MicroMipsSizeReduction.cpp -SRCS_MIN+= Target/Mips/Mips16FrameLowering.cpp -SRCS_MIN+= Target/Mips/Mips16HardFloat.cpp -SRCS_MIN+= Target/Mips/Mips16HardFloatInfo.cpp -SRCS_MIN+= Target/Mips/Mips16ISelDAGToDAG.cpp -SRCS_MIN+= Target/Mips/Mips16ISelLowering.cpp -SRCS_MIN+= Target/Mips/Mips16InstrInfo.cpp -SRCS_MIN+= Target/Mips/Mips16RegisterInfo.cpp -SRCS_MIN+= Target/Mips/MipsAnalyzeImmediate.cpp -SRCS_MIN+= Target/Mips/MipsAsmPrinter.cpp -SRCS_MIN+= Target/Mips/MipsBranchExpansion.cpp -SRCS_MIN+= Target/Mips/MipsCCState.cpp -SRCS_MIN+= Target/Mips/MipsCallLowering.cpp -SRCS_MIN+= Target/Mips/MipsConstantIslandPass.cpp -SRCS_MIN+= Target/Mips/MipsDelaySlotFiller.cpp -SRCS_MIN+= Target/Mips/MipsExpandPseudo.cpp -SRCS_MIN+= Target/Mips/MipsFastISel.cpp -SRCS_MIN+= Target/Mips/MipsFrameLowering.cpp -SRCS_MIN+= Target/Mips/MipsISelDAGToDAG.cpp -SRCS_MIN+= Target/Mips/MipsISelLowering.cpp -SRCS_MIN+= Target/Mips/MipsInstrInfo.cpp -SRCS_MIN+= Target/Mips/MipsInstructionSelector.cpp -SRCS_MIN+= Target/Mips/MipsLegalizerInfo.cpp -SRCS_MIN+= Target/Mips/MipsMCInstLower.cpp -SRCS_MIN+= Target/Mips/MipsMachineFunction.cpp -SRCS_MIN+= Target/Mips/MipsModuleISelDAGToDAG.cpp -SRCS_MIN+= Target/Mips/MipsMulMulBugPass.cpp -SRCS_MIN+= Target/Mips/MipsOptimizePICCall.cpp -SRCS_MIN+= Target/Mips/MipsOs16.cpp -SRCS_MIN+= Target/Mips/MipsPostLegalizerCombiner.cpp -SRCS_MIN+= Target/Mips/MipsPreLegalizerCombiner.cpp -SRCS_MIN+= Target/Mips/MipsRegisterBankInfo.cpp -SRCS_MIN+= Target/Mips/MipsRegisterInfo.cpp -SRCS_MIN+= Target/Mips/MipsSEFrameLowering.cpp -SRCS_MIN+= Target/Mips/MipsSEISelDAGToDAG.cpp -SRCS_MIN+= Target/Mips/MipsSEISelLowering.cpp -SRCS_MIN+= Target/Mips/MipsSEInstrInfo.cpp -SRCS_MIN+= Target/Mips/MipsSERegisterInfo.cpp -SRCS_MIN+= Target/Mips/MipsSubtarget.cpp -SRCS_MIN+= Target/Mips/MipsTargetMachine.cpp -SRCS_MIN+= Target/Mips/MipsTargetObjectFile.cpp -SRCS_MIN+= Target/Mips/MipsTargetTransformInfo.cpp -SRCS_MIN+= Target/Mips/TargetInfo/MipsTargetInfo.cpp -.endif # MK_LLVM_TARGET_MIPS .if ${MK_LLVM_TARGET_POWERPC} != "no" SRCS_MIN+= Target/PowerPC/AsmParser/PPCAsmParser.cpp SRCS_MIN+= Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -2331,8 +2271,7 @@ beforebuild: # Note: some rules are superfluous, not every combination is valid. .for arch in \ - AArch64/AArch64 ARM/ARM BPF/BPF Mips/Mips PowerPC/PPC RISCV/RISCV \ - X86/X86 + AArch64/AArch64 ARM/ARM BPF/BPF PowerPC/PPC RISCV/RISCV X86/X86 . for hdr in \ AsmMatcher/-gen-asm-matcher \ AsmWriter/-gen-asm-writer \ @@ -2425,22 +2364,6 @@ TGHDRS+= BPFGenRegisterBank.inc TGHDRS+= BPFGenRegisterInfo.inc TGHDRS+= BPFGenSubtargetInfo.inc .endif # MK_LLVM_TARGET_BPF -.if ${MK_LLVM_TARGET_MIPS} != "no" -TGHDRS+= MipsGenAsmMatcher.inc -TGHDRS+= MipsGenAsmWriter.inc -TGHDRS+= MipsGenCallingConv.inc -TGHDRS+= MipsGenDAGISel.inc -TGHDRS+= MipsGenDisassemblerTables.inc -TGHDRS+= MipsGenFastISel.inc -TGHDRS+= MipsGenGlobalISel.inc -TGHDRS+= MipsGenInstrInfo.inc -TGHDRS+= MipsGenMCCodeEmitter.inc -TGHDRS+= MipsGenMCPseudoLowering.inc -TGHDRS+= MipsGenPostLegalizeGICombiner.inc -TGHDRS+= MipsGenRegisterBank.inc -TGHDRS+= MipsGenRegisterInfo.inc -TGHDRS+= MipsGenSubtargetInfo.inc -.endif # MK_LLVM_TARGET_MIPS .if ${MK_LLVM_TARGET_POWERPC} != "no" TGHDRS+= PPCGenAsmMatcher.inc TGHDRS+= PPCGenAsmWriter.inc diff --git a/lib/clang/llvm.build.mk b/lib/clang/llvm.build.mk index b8b4be7dfe28..d06a2f42479c 100644 --- a/lib/clang/llvm.build.mk +++ b/lib/clang/llvm.build.mk @@ -71,9 +71,6 @@ LLVM_NATIVE_ARCH= ARM .if ${MK_LLVM_TARGET_BPF} != "no" CFLAGS+= -DLLVM_TARGET_ENABLE_BPF .endif -.if ${MK_LLVM_TARGET_MIPS} != "no" -CFLAGS+= -DLLVM_TARGET_ENABLE_MIPS -.endif .if ${MK_LLVM_TARGET_POWERPC} != "no" CFLAGS+= -DLLVM_TARGET_ENABLE_POWERPC . if ${MACHINE_CPUARCH} == "powerpc" diff --git a/share/man/man5/src.conf.5 b/share/man/man5/src.conf.5 index 10bf73581dc0..37747ac4fb53 100644 --- a/share/man/man5/src.conf.5 +++ b/share/man/man5/src.conf.5 @@ -1,5 +1,5 @@ .\" DO NOT EDIT-- this file is @generated by tools/build/options/makeman. -.Dd September 21, 2026 +.Dd September 24, 2026 .Dt SRC.CONF 5 .Os .Sh NAME @@ -1043,11 +1043,6 @@ Build LLVM target support for BPF. The .Va LLVM_TARGET_ALL option should be used rather than this in most cases. -.It Va WITH_LLVM_TARGET_MIPS -Build LLVM target support for MIPS. -The -.Va LLVM_TARGET_ALL -option should be used rather than this in most cases. .It Va WITHOUT_LLVM_TARGET_POWERPC Do not build LLVM target support for PowerPC. The diff --git a/share/mk/src.opts.mk b/share/mk/src.opts.mk index 0c6b97461b5e..8ca5fbd1873b 100644 --- a/share/mk/src.opts.mk +++ b/share/mk/src.opts.mk @@ -293,7 +293,7 @@ __DEFAULT_DEPENDENT_OPTIONS+= LLVM_TARGET_${__llt:${__LLVM_TARGET_FILT}:tu}/LLVM .endif .endfor -__DEFAULT_NO_OPTIONS+=LLVM_TARGET_BPF LLVM_TARGET_MIPS +__DEFAULT_NO_OPTIONS+=LLVM_TARGET_BPF .include diff --git a/tools/build/options/WITHOUT_LLVM_TARGET_MIPS b/tools/build/options/WITHOUT_LLVM_TARGET_MIPS deleted file mode 100644 index 2b8218b2c8c4..000000000000 --- a/tools/build/options/WITHOUT_LLVM_TARGET_MIPS +++ /dev/null @@ -1,4 +0,0 @@ -Do not build LLVM target support for MIPS. -The -.Va LLVM_TARGET_ALL -option should be used rather than this in most cases. diff --git a/tools/build/options/WITH_LLVM_TARGET_MIPS b/tools/build/options/WITH_LLVM_TARGET_MIPS deleted file mode 100644 index 4cc2a85cd34c..000000000000 --- a/tools/build/options/WITH_LLVM_TARGET_MIPS +++ /dev/null @@ -1,4 +0,0 @@ -Build LLVM target support for MIPS. -The -.Va LLVM_TARGET_ALL -option should be used rather than this in most cases.