From nobody Wed Sep 09 14:23:01 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4hg31f19XVz6s9yx for ; Wed, 09 Sep 2026 14:23:02 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4hg31f043sz3K51 for ; Wed, 09 Sep 2026 14:23:02 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1788963782; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=WxigtShBvYD8AnOKRbA9CxgtDSuOj2sU2B0GoPjYXnE=; b=ATVHcazb3Y0uZ2Q8z+r51gh9qh0G/ZIN77jN1+NBxUN3aanaGRd3jeyXamKCIv9fCh5GBN sRY0/qruYZIwQbvhT3qjFzo5xPA7othnMZhJWKOtLJrJ4okVZ7gVaNSFwf8wIDdnXA19rN tD3aXHiDbTLKJX5KGQ6y02u6VEXwKwIDBlkjDGuWco2pxXjJKdzO/7Wkl0QPLh6dYubqpX Qoh9gPeDCZP8xiW40GA9HRITs9MOPt45DwwoB1OSXDG5jXGJpOm/SFrD0BmaCiB44V9a5N IjUk5ieKSlgHeLTZj2INAMs7BK76TgP/ya/0GY/TlNNTOK5YPrfewXnykpKNnA== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1788963782; b=N+iL08khPaO3FdQipg8g3+6QnY7HuvB12dq84GCd3CXIZYiRZ2ejnHgajBkdKKh943gBZ/ ravXvTkBsuthYbmZnp9ZWMADV/X532Vk5f9JEZeaFRK08fI6lsPBlJBJjXeKaaxthn1Chx 3dD7UobieepmuFMY0nLCWMxkNV4y7vvw9FmA6/EsY7zLB15Hojw8+0sc+gaBy+NLwGbEJi uor0CyTOkwNEAMKL83s0cSwQ6w8JrMsNiWfaln1GoBnCfh3HL45n1hVPKyTDR5160th80Z ZTXgF9d27GM70KABbNzMclgFQlAWTWXeG9FebctEgEbx5Gr/64kvp7quyHJ3aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1788963782; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=WxigtShBvYD8AnOKRbA9CxgtDSuOj2sU2B0GoPjYXnE=; b=i23cOXZK5UCRIJt50cCEpnEJbJHpArhI1HA4rPbp40zDgaQNgPaGPQVCcLKocExhjkGaMX MnAjo7nntd9hdeHXO8DbBQmWFzJbTFvVHg9aRhYQ7Mzjib/XzCPlQZ+J4AiSei256D6p5O ftoQW+n0OAgcTMW91Bh4D4mv159ukLLRYEw93hjIhhmeMQSsx2+WoxPwXJkdfkZDhMESEC IlO0566MgH53YAwZ5uDjiW+bTZ/KWf7MNN46+OXjwP3AyQ81igDUgvjmej2oCHwxSFssqx g5zXsL8dMq4luC4D/77s1teAuoshK/4JCpKhhcjzCFjSUXOUKGHYsjjX2LmVnQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4hg31d64PSz11Bt for ; Wed, 09 Sep 2026 14:23:01 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 18219 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Wed, 09 Sep 2026 14:23:01 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: e1f684a16036 - main - arm64: Fix the ICC_SGI1R_EL1 field names List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: e1f684a1603618b63640bcaf35da6e14ef3edb54 Auto-Submitted: auto-generated Date: Wed, 09 Sep 2026 14:23:01 +0000 Message-Id: <6aa16bc5.18219.7da1a31b@gitrepo.freebsd.org> The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=e1f684a1603618b63640bcaf35da6e14ef3edb54 commit e1f684a1603618b63640bcaf35da6e14ef3edb54 Author: Andrew Turner AuthorDate: 2026-09-07 23:29:49 +0000 Commit: Andrew Turner CommitDate: 2026-09-08 03:05:27 +0000 arm64: Fix the ICC_SGI1R_EL1 field names Use the field names from the Arm Documentation for the ICC_SGI1R_EL1 register. These will later be generated from a BSD Licensed JSON file so to reduce the diff for that rename now. Reviewed by: Kajetan Puchalski Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D59174 --- sys/arm64/arm64/gic_v3.c | 8 ++++---- sys/arm64/include/armreg.h | 38 +++++++++++++++++++------------------- sys/arm64/vmm/io/vgic_v3.c | 15 ++++++++------- 3 files changed, 31 insertions(+), 30 deletions(-) diff --git a/sys/arm64/arm64/gic_v3.c b/sys/arm64/arm64/gic_v3.c index 3d9f5f2628fb..3f6b0f1f1c0a 100644 --- a/sys/arm64/arm64/gic_v3.c +++ b/sys/arm64/arm64/gic_v3.c @@ -1177,13 +1177,13 @@ gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, /* Send the IPI to this cpu */ if (CPU_ISSET(i, &cpus)) { #define ICC_SGI1R_AFFINITY(aff) \ - (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) | \ - ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) | \ - ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT)) + (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_Aff3_SHIFT) | \ + ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_Aff2_SHIFT) | \ + ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_Aff1_SHIFT)) /* Set the affinity when the first at this level */ if (val == 0) val = ICC_SGI1R_AFFINITY(aff) | - irq << ICC_SGI1R_EL1_SGIID_SHIFT; + irq << ICC_SGI1R_INTID_SHIFT; /* Set the bit to send the IPI to te CPU */ val |= 1 << CPU_AFF0(CPU_AFFINITY(i)); } diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 779485dfa61c..9db452314977 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -830,25 +830,25 @@ #define ICC_SGI1R_EL1_CRn 12 #define ICC_SGI1R_EL1_CRm 11 #define ICC_SGI1R_EL1_op2 5 -#define ICC_SGI1R_EL1_TL_SHIFT 0 -#define ICC_SGI1R_EL1_TL_MASK (0xffffUL << ICC_SGI1R_EL1_TL_SHIFT) -#define ICC_SGI1R_EL1_TL_VAL(x) ((x) & ICC_SGI1R_EL1_TL_MASK) -#define ICC_SGI1R_EL1_AFF1_SHIFT 16 -#define ICC_SGI1R_EL1_AFF1_MASK (0xfful << ICC_SGI1R_EL1_AFF1_SHIFT) -#define ICC_SGI1R_EL1_AFF1_VAL(x) ((x) & ICC_SGI1R_EL1_AFF1_MASK) -#define ICC_SGI1R_EL1_SGIID_SHIFT 24 -#define ICC_SGI1R_EL1_SGIID_MASK (0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT) -#define ICC_SGI1R_EL1_SGIID_VAL(x) ((x) & ICC_SGI1R_EL1_SGIID_MASK) -#define ICC_SGI1R_EL1_AFF2_SHIFT 32 -#define ICC_SGI1R_EL1_AFF2_MASK (0xfful << ICC_SGI1R_EL1_AFF2_SHIFT) -#define ICC_SGI1R_EL1_AFF2_VAL(x) ((x) & ICC_SGI1R_EL1_AFF2_MASK) -#define ICC_SGI1R_EL1_RS_SHIFT 44 -#define ICC_SGI1R_EL1_RS_MASK (0xful << ICC_SGI1R_EL1_RS_SHIFT) -#define ICC_SGI1R_EL1_RS_VAL(x) ((x) & ICC_SGI1R_EL1_RS_MASK) -#define ICC_SGI1R_EL1_AFF3_SHIFT 48 -#define ICC_SGI1R_EL1_AFF3_MASK (0xfful << ICC_SGI1R_EL1_AFF3_SHIFT) -#define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK) -#define ICC_SGI1R_EL1_IRM (0x1UL << 40) +#define ICC_SGI1R_TargetList_SHIFT 0 +#define ICC_SGI1R_TargetList_MASK (0xffffUL << ICC_SGI1R_TargetList_SHIFT) +#define ICC_SGI1R_TargetList_VAL(x) ((x) & ICC_SGI1R_TargetList_MASK) +#define ICC_SGI1R_Aff1_SHIFT 16 +#define ICC_SGI1R_Aff1_MASK (0xfful << ICC_SGI1R_Aff1_SHIFT) +#define ICC_SGI1R_Aff1_VAL(x) ((x) & ICC_SGI1R_Aff1_MASK) +#define ICC_SGI1R_INTID_SHIFT 24 +#define ICC_SGI1R_INTID_MASK (0xfUL << ICC_SGI1R_INTID_SHIFT) +#define ICC_SGI1R_INTID_VAL(x) ((x) & ICC_SGI1R_INTID_MASK) +#define ICC_SGI1R_Aff2_SHIFT 32 +#define ICC_SGI1R_Aff2_MASK (0xfful << ICC_SGI1R_Aff2_SHIFT) +#define ICC_SGI1R_Aff2_VAL(x) ((x) & ICC_SGI1R_Aff2_MASK) +#define ICC_SGI1R_IRM (0x1UL << 40) +#define ICC_SGI1R_RS_SHIFT 44 +#define ICC_SGI1R_RS_MASK (0xful << ICC_SGI1R_RS_SHIFT) +#define ICC_SGI1R_RS_VAL(x) ((x) & ICC_SGI1R_RS_MASK) +#define ICC_SGI1R_Aff3_SHIFT 48 +#define ICC_SGI1R_Aff3_MASK (0xfful << ICC_SGI1R_Aff3_SHIFT) +#define ICC_SGI1R_Aff3_VAL(x) ((x) & ICC_SGI1R_Aff3_MASK) /* ICC_SRE_EL1 */ #define ICC_SRE_EL1_SRE (1U << 0) diff --git a/sys/arm64/vmm/io/vgic_v3.c b/sys/arm64/vmm/io/vgic_v3.c index ff7a2a9a761f..bc5d4403b1a0 100644 --- a/sys/arm64/vmm/io/vgic_v3.c +++ b/sys/arm64/vmm/io/vgic_v3.c @@ -1624,19 +1624,20 @@ vgic_v3_icc_sgi1r_write(struct vcpu *vcpu, uint64_t rval, void *arg) active_cpus = vm_active_cpus(vm); vcpuid = vcpu_vcpuid(vcpu); - irqid = ICC_SGI1R_EL1_SGIID_VAL(rval) >> ICC_SGI1R_EL1_SGIID_SHIFT; - if ((rval & ICC_SGI1R_EL1_IRM) == 0) { + irqid = ICC_SGI1R_INTID_VAL(rval) >> ICC_SGI1R_INTID_SHIFT; + if ((rval & ICC_SGI1R_IRM) == 0) { /* Non-zero points at no vcpus */ - if (ICC_SGI1R_EL1_RS_VAL(rval) != 0) + if (ICC_SGI1R_RS_VAL(rval) != 0) return (0); - aff1 = ICC_SGI1R_EL1_AFF1_VAL(rval) >> ICC_SGI1R_EL1_AFF1_SHIFT; - aff2 = ICC_SGI1R_EL1_AFF2_VAL(rval) >> ICC_SGI1R_EL1_AFF2_SHIFT; - aff3 = ICC_SGI1R_EL1_AFF3_VAL(rval) >> ICC_SGI1R_EL1_AFF3_SHIFT; + aff1 = ICC_SGI1R_Aff1_VAL(rval) >> ICC_SGI1R_Aff1_SHIFT; + aff2 = ICC_SGI1R_Aff2_VAL(rval) >> ICC_SGI1R_Aff2_SHIFT; + aff3 = ICC_SGI1R_Aff3_VAL(rval) >> ICC_SGI1R_Aff3_SHIFT; mpidr = aff3 << MPIDR_AFF3_SHIFT | aff2 << MPIDR_AFF2_SHIFT | aff1 << MPIDR_AFF1_SHIFT; - cpus = ICC_SGI1R_EL1_TL_VAL(rval) >> ICC_SGI1R_EL1_TL_SHIFT; + cpus = ICC_SGI1R_TargetList_VAL(rval) >> + ICC_SGI1R_TargetList_SHIFT; cpu_off = 0; while (cpus > 0) { if (cpus & 1) {