From nobody Sat Sep 05 04:15:14 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4hcKkB4pN6z6qryc for ; Sat, 05 Sep 2026 04:15:14 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4hcKkB1bwnz3bgd for ; Sat, 05 Sep 2026 04:15:14 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1788581714; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=rM0dPDplHCgvWmSfmQwzVtAHWEUmXqR+40UnWy08Xjg=; b=OX1bTrVs/G+fJ2ozg3isyiCwY3zpFcU5yQEfpvhubcZRj0n69FcBvJAdv/YlAUWc8zX+KH mykxy1/28ttZ3wG9bFWYegx+SsZtJj+6VpkmCHMXsuAL2xTWv9OGJZv8WKGlaravpvvfs3 TWQjgfhEeGBnYQevdFO7D//oUpQUsBnxNgf9CPE09NGh5cbzXkrx+zSS3/v5qYGOSmS3aQ RAnHC2/x9S2Wk9y8I7ryklFfn9PF3OC9+GozWEWG3vW1n4EfIQaoej/JSRh5jgaBhWLV2J wp4UteLeRDN16Rx2slVico40gHwSuQ7pjfL59qC2ezoa9rnasHtpNZzHChRdbg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1788581714; a=rsa-sha256; cv=none; b=sLjnnyyWs6IKhiDFQo0RXVO3Fsom2nKLNFZdSrO1rmOqrBNS0n/2dTS69mASS8pGpc2ISQ iWdJYis3JfRPmejYf8MfpenWHGAmfb9k+2Ulp097/S3zLpJhuNOIaPa3om7vX8WO9eWfvK e1DeJyQXt83a5eGSoGfUuGKRKZ3LiTbiC11LDa8nm4MxADkKZkLyHYvDaBWjgMr2FeDn51 UnjV8+v4clbCjLPlWmCS3K90aFDGpO3BTTHQGjpZidTuU5DY1tAPIjgcKRiAHPFNZKX7FR mUTEYwOCsmb1fN1nQk7OtuOFPZejnaKcRMcVNxEE1n3QheQA5O3si3sNN/nDzA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1788581714; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=rM0dPDplHCgvWmSfmQwzVtAHWEUmXqR+40UnWy08Xjg=; b=SeMiCyYSuS8Y4whX/PkN17U3ONN3EV0otrPCQRMTQ64c9Tn+Apzy2Uf6t+cJx3WxJbZWbP +K27767hIAigyGF4HzaDx/ZbhpklU5iJt+8WJoYXhacMdq4Z/p24Is7wlX0uUwEqdGQpN6 hUOSrh7PFLFK03cUmof4L44BcjUapSXsGHDS+qFZL37s8I3TE4ud8eX5+6fXlls0iEm5VI 0dEKVymkEbqvcu2lS0diLp9ChIQGdveVGWcukwDoJ4bMs/tdrVmAQ+bz/sk/h4o61Jamws HFY8PTWmmxcxh1zVU8NWJIUjCz9vh8cyakCqetz1jElVYPLq3qnZA1+tCFQRew== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4hcKkB08PJzW0n for ; Sat, 05 Sep 2026 04:15:14 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 3ef4c by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Sat, 05 Sep 2026 04:15:14 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Justin Hibbits Subject: git: 42f9049ab8d6 - main - powerpc/watchdog: Make e500 watchdog action tunable List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jhibbits X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 42f9049ab8d69900b395381d72101ab703b9fe87 Auto-Submitted: auto-generated Date: Sat, 05 Sep 2026 04:15:14 +0000 Message-Id: <6a9b9752.3ef4c.62035308@gitrepo.freebsd.org> The branch main has been updated by jhibbits: URL: https://cgit.FreeBSD.org/src/commit/?id=42f9049ab8d69900b395381d72101ab703b9fe87 commit 42f9049ab8d69900b395381d72101ab703b9fe87 Author: Justin Hibbits AuthorDate: 2026-09-05 04:09:07 +0000 Commit: Justin Hibbits CommitDate: 2026-09-05 04:09:07 +0000 powerpc/watchdog: Make e500 watchdog action tunable There are 4 options for e500 watchdog timeout, which may be core- or even SoC- specific. Add support to tune the behavior via a tunable (machdep.watchdog_mode). The tunable value is an integer 0-3. --- sys/powerpc/booke/machdep_e500.c | 9 +++++++-- sys/powerpc/include/spr.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/sys/powerpc/booke/machdep_e500.c b/sys/powerpc/booke/machdep_e500.c index 2f39a66aac6d..92e0f8387865 100644 --- a/sys/powerpc/booke/machdep_e500.c +++ b/sys/powerpc/booke/machdep_e500.c @@ -148,6 +148,10 @@ cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode) * * With all PowerPC numbering, 0 is the MSB, and 63 is LSB. */ +/* Default watchdog_mode to chip reset (2). */ +static int watchdog_mode = (TCR_WRC_CHIP >> TCR_WRC_SHIFT); + +TUNABLE_INT("machdep.watchdog_mode", &watchdog_mode); /* Arg is the timebase bit number 1-based (flsll result) */ static void booke_watchdog_cpu(void *arg) @@ -162,7 +166,8 @@ booke_watchdog_cpu(void *arg) tcr &= ~(TCR_WP_MASK | TCR_WPEXT_MASK); tcr |= TCR_MAKE_WP(bitno); - tcr |= TCR_WRC_CHIP | TCR_WIE; + tcr |= ((watchdog_mode << TCR_WRC_SHIFT) & TCR_WRC_MASK); + tcr |= TCR_WIE; mtspr(SPR_TCR, tcr); } @@ -190,7 +195,7 @@ booke_watchdog_fn(void *priv, sbintime_t sbt, sbintime_t *esbt, int *err) * count, using only a mask of the current timebase matching the tick * size. This will give us the next rollover bit *beyond* the timeout. */ - tb = mftb() & ((1 << flsll(ticks)) - 1); + tb = mftb() & ((1ULL << flsll(ticks)) - 1); tb += ticks; tb_bit = 64 - flsll(tb); diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h index 40911a7c293d..2104c08bd296 100644 --- a/sys/powerpc/include/spr.h +++ b/sys/powerpc/include/spr.h @@ -539,6 +539,7 @@ #define TCR_WRC_CORE 0x10000000 /* Core reset */ #define TCR_WRC_CHIP 0x20000000 /* Chip reset */ #define TCR_WRC_SYSTEM 0x30000000 /* System reset */ +#define TCR_WRC_SHIFT 28 #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ #define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */