From nobody Mon Oct 26 15:02:38 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4jCxgf59Lpz6wqXX for ; Mon, 26 Oct 2026 15:02:38 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 4jCxgf2sSHz4pdJ for ; Mon, 26 Oct 2026 15:02:38 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1793026958; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=NEEVQCv2VnoZkwgsercy1bYteY8pODjSH/dEQv1eMuQ=; b=uYYcGKyVdMGtgIuUy+92X4HRr7JClgZ/IJJlSshe1eeJ+lrTCNwHnlgUG5AOiguACiRaCe exFXgt+KY4hzIx9X0UWLRUrSWsBg2tTBzBl0sP+AdvwL41h5heWVIid+LE8ZfimBri1ytp iTJlwHz7est/kEnIAjbebWaUdMY7hJOieJnbffBCcNqJbvMCIfB6YrvT+uqyt/gEdgXwEp fiJ7ZQATeaJlkDYYBxmTAF+C63q1EF711inf+RWwxqa28956sh+/kjLCo5VGHi6sznMiCW xEYi8ng0gaA/ONqcFt9VB53Jc/RjqQhFegxN4Em1ATGPnTIs2rEz72KtN5U6WA== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1793026958; b=tcrbklb7oFrfrpMqzmgYvESlEYooohUDHg0OjL5m9aMD4iLq2gU+p+khfp7ir/FoxuJeIk 5p7ImX+vdDJG5UiVAOWUFYpcrbvGrpzosCiCu27VRdepo0M+FfIejkFMtJKkaLYwdytWBK oPhzUtHxQykbZsyWGxz33fy1WotBWoqLGe3/IIdkg/Zd2UWJaA28TWJdhQce5ar54rxa9H ziW9RaLBToBjQ/dygp6J9F7pPEnW8Uxju24Ao61BglqPviGCFlsbheMBmSxDdXCq5THBKQ J/cW+ngMAZPlsZpr6zIcoXgVukPjdkWdyFvnkzn/YFa1rKAdX+WdiTupHp1KLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1793026958; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=NEEVQCv2VnoZkwgsercy1bYteY8pODjSH/dEQv1eMuQ=; b=tLZLDI958GrkEZgYhW1WIrbc7P+mdSzEG7nS0rrx525ytw3GX2TSYZKlU2Wk4WLSeiGQ6h 1fFnJ+8U4HsYEKrcus91djXmGrAN8bGMGk0w7L2UYpYXqN0fUpQOZWpedu5n7k9TgirgKU BGlcSmDjY9c+u/Nb0y4bXCdPRepy6gPwEIZ61CvMn+24MRJkFNpUgdswtFrMjKU42NVtFH bdhLDKCinsESPyGVm4OoDnPexF1IzJQpLdQy2caWeTx+1Kfgv8Hefe0QjUpykcnG+7TUYc 5ti8TKZaHGYdbhjQiGR8RrPzeXbFJ/qz8+GU0Mwoca43t7fOrobrOLaA92/GPg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4jCxgf2XCQzfqf for ; Mon, 26 Oct 2026 15:02:38 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 4183e by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Mon, 26 Oct 2026 15:02:38 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Cc: Rick Richard From: Mitchell Horne Subject: git: 509d65fae512 - main - riscv: Map the DTB when it is outside the kernel's 1GB region List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org List-Id: Commit messages for all branches of the src repository List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 509d65fae512c24fc755d6a8b3b41bb967e6c5e1 Auto-Submitted: auto-generated Date: Mon, 26 Oct 2026 15:02:38 +0000 Message-Id: <6adf6b8e.4183e.2346b336@gitrepo.freebsd.org> The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=509d65fae512c24fc755d6a8b3b41bb967e6c5e1 commit 509d65fae512c24fc755d6a8b3b41bb967e6c5e1 Author: Rick Richard AuthorDate: 2026-10-03 16:00:00 +0000 Commit: Mitchell Horne CommitDate: 2026-10-26 15:01:39 +0000 riscv: Map the DTB when it is outside the kernel's 1GB region When the kernel is started directly by SBI firmware, locore.S maps only the 1GB region that contains the kernel, and initriscv() reads the DTB through that mapping at the physical address passed in a1. If the firmware put the DTB in another 1GB region, as QEMU does with more than 1GB of RAM, fake_preload_metadata() faults before the console is up and the kernel hangs. Also map the 1GB region that contains the DTB. This fixes direct kernel booting without FreeBSD loader(8). PR: 299088 Reviewed by: mhorne Fixes: bfb857546984 ("riscv: Construct an identity map in locore.S") MFC after: 1 week Signed-off-by: Rick Richard --- sys/riscv/riscv/locore.S | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/sys/riscv/riscv/locore.S b/sys/riscv/riscv/locore.S index e2126af5cad2..b4ab4aa43ff8 100644 --- a/sys/riscv/riscv/locore.S +++ b/sys/riscv/riscv/locore.S @@ -127,7 +127,8 @@ _start: * starting from the first 2MB physical page into which the kernel was * loaded. * - * We also use an L1 entry to create a 1GB identity map (1:1 PA->VA). + * We also use L1 entries to create 1GB identity maps (1:1 PA->VA) + * of the regions holding the kernel and the DTB. * This is useful for two reasons: * - handling the DTB pointer passed from SBI firmware (physical addr) * - simpler construction of pagetables in pmap_bootstrap() @@ -162,6 +163,17 @@ pagetables: add t0, s1, a5 sd t6, (t0) /* Store new PTE */ + /* Identity map the DTB's 1GB region too, if we were given a DTB */ + beqz s4, 1f + srli s2, s4, L1_SHIFT /* dtbp >> L1_SHIFT */ + andi a5, s2, Ln_ADDR_MASK /* & Ln_ADDR_MASK */ + slli s2, s2, PTE_PPN2_S /* (s2 << PTE_PPN2_S) */ + or t6, t4, s2 + mulw a5, a5, a6 /* calculate L1 slot */ + add t0, s1, a5 + sd t6, (t0) /* Store new PTE */ +1: + /* Construct the virtual address space at KERNBASE */ /* Add L1 entry for kernel */ @@ -189,14 +201,14 @@ pagetables: add t3, t4, t2 li t0, (PTE_KERN | PTE_X) or t0, t0, s8 /* t0 |= pte bits */ -1: +2: slli t2, t4, PTE_PPN1_S /* << PTE_PPN1_S */ or t5, t0, t2 sd t5, (s1) /* Store PTE entry to position */ addi s1, s1, PTE_SIZE addi t4, t4, 1 - bltu t4, t3, 1b + bltu t4, t3, 2b /* Page tables END */