From nobody Tue Oct 06 07:50:56 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4hzT2n1BXXz6cWDJ for ; Tue, 06 Oct 2026 07:50:57 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4hzT2n054xz4Ft5 for ; Tue, 06 Oct 2026 07:50:57 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791273057; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=FFPVmulhC66rP0f4zxor6u/YVi0cac2bFEnNcw6RTZ4=; b=VAcXfqRHVpUjY10thFmP2mFm/HjJlBy/DN0jEC/4hkGphtUrkf7wwnyIeJy7NJBHXdi68r 5aJlvG/gSlWTS77pMIU6GjCO8g3y8dYL4p3xXjbZPmtds2OsIcH8Rax9/omdNRFya0kl48 F0VOz77Xzp3jUsB1UzmKk8z0wYFKIcn5hjcmYeJ4te5u0EHm7km0EkkwrxIYp/qhF1yjJl DKvXJK6qRsrirypFC3XLIKwPHrJUP/dqXpyubeG6/uG0EzeSf1Z8aHaSDBbm7XEcWLwMW9 jve5L7iqFX5t2svRWwkUExKEFUWlqG52bwnUmQNxBo2fWnZygy22EL3g3VlvZQ== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1791273057; b=HWm/t4v6i4m3HIpXF0N3vk706m5N6x2ZC3XsSz9WyI8YplvRb33Z6RaeXxJb/8JVd8q0P5 8H1EY4gJwPH5wxsw58AGAEBrgBmOBpObuVou3Qw0Wq4ll1B/p/uKYI6Sqoa34exWdWDO41 KeiqAfd4jyDQCSlIRZXUozgVgFa0WHPxWay6+Gug1LEs0NQvT14BAVLCS9z7L2DBFM7lEr e5iNWEidATOnU75yQhNWwXT3cnUELeIPx1Ldcdaw3l1aLR6t+KejR0KncCgMRAib7JISMp mFXo7FrbgLhq56AvOxOBdrvwa9qa0DpGyCUOZxzGpKkzTVYu33n1bJ+V32x52g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791273057; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=FFPVmulhC66rP0f4zxor6u/YVi0cac2bFEnNcw6RTZ4=; b=WGnew8p2h2UfXXS2OebM2aKuWw2CITJPU4mzkspvSuYa+kdQdPdspqOlPE4CXZCd6xoZN1 nvlzyurwgfGVIcpr7V/aRqXIXLdxK144MjwiIYLcuCmp/aQITKrn9pzsTNqz0lyOObAOVb Y+YH7uX6agVn/kHt/xL7PzJ9LOfDtXwnjCGoxogxXFJqikdhJwH9KwYN0SvwoMlWPsqrJi qkV88fKv236BX2z4LsUGdNdGXdDrUaLABarVX/W2MZgBW2OwpcDN2PGYhR1Gcqxa5uUtgp WMyY91Oo0WxzvfqcnbNvsfD615xNQAEHGYQzS7EPNpqiuYCCcW1yGRVngsaA4A== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4hzT2m66MTzxZ5 for ; Tue, 06 Oct 2026 07:50:56 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 473f4 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Tue, 06 Oct 2026 07:50:56 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Jaeyoon Choi Subject: git: 5286fdbc8e97 - stable/15 - ufshci: fix bug in ufshci_req_sdb_enable List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jaeyoon X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: 5286fdbc8e977f1b8cb8ed4153cf01b5648e0dde Auto-Submitted: auto-generated Date: Tue, 06 Oct 2026 07:50:56 +0000 Message-Id: <6ac4a860.473f4.6cd2648@gitrepo.freebsd.org> The branch stable/15 has been updated by jaeyoon: URL: https://cgit.FreeBSD.org/src/commit/?id=5286fdbc8e977f1b8cb8ed4153cf01b5648e0dde commit 5286fdbc8e977f1b8cb8ed4153cf01b5648e0dde Author: Jaeyoon Choi AuthorDate: 2026-03-24 05:12:14 +0000 Commit: Jaeyoon Choi CommitDate: 2026-10-06 06:27:51 +0000 ufshci: fix bug in ufshci_req_sdb_enable When enabling the request queue, safely reset the list base address. This was added due to a quirk in the Qualcomm UFS controller during the process of activating it. Sponsored by: Samsung Electronics Reviewed by: imp (mentor) Differential Revision: https://reviews.freebsd.org/D55984 (cherry picked from commit c4386988baa2ecdcb482c8ccace183dc643d097c) --- sys/dev/ufshci/ufshci_req_sdb.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/sys/dev/ufshci/ufshci_req_sdb.c b/sys/dev/ufshci/ufshci_req_sdb.c index ca47aa159c5b..54542f48b32c 100644 --- a/sys/dev/ufshci/ufshci_req_sdb.c +++ b/sys/dev/ufshci/ufshci_req_sdb.c @@ -374,34 +374,63 @@ ufshci_req_sdb_enable(struct ufshci_controller *ctrlr, struct ufshci_req_queue *req_queue) { struct ufshci_hw_queue *hwq = &req_queue->hwq[UFSHCI_SDB_Q]; + int error = 0; + + mtx_lock(&hwq->recovery_lock); + mtx_lock(&hwq->qlock); if (req_queue->is_task_mgmt) { uint32_t hcs, utmrldbr, utmrlrsr; + uint32_t utmrlba, utmrlbau; + + /* + * Some controllers require re-enabling. When a controller is + * re-enabled, the utmrlba registers are initialized, and these + * must be reconfigured upon re-enabling. + */ + utmrlba = hwq->req_queue_addr & 0xffffffff; + utmrlbau = hwq->req_queue_addr >> 32; + ufshci_mmio_write_4(ctrlr, utmrlba, utmrlba); + ufshci_mmio_write_4(ctrlr, utmrlbau, utmrlbau); hcs = ufshci_mmio_read_4(ctrlr, hcs); if (!(hcs & UFSHCIM(UFSHCI_HCS_REG_UTMRLRDY))) { ufshci_printf(ctrlr, "UTP task management request list is not ready\n"); - return (ENXIO); + error = ENXIO; + goto out; } utmrldbr = ufshci_mmio_read_4(ctrlr, utmrldbr); if (utmrldbr != 0) { ufshci_printf(ctrlr, "UTP task management request list door bell is not ready\n"); - return (ENXIO); + error = ENXIO; + goto out; } utmrlrsr = UFSHCIM(UFSHCI_UTMRLRSR_REG_UTMRLRSR); ufshci_mmio_write_4(ctrlr, utmrlrsr, utmrlrsr); } else { uint32_t hcs, utrldbr, utrlcnr, utrlrsr; + uint32_t utrlba, utrlbau; + + /* + * Some controllers require re-enabling. When a controller is + * re-enabled, the utrlba registers are initialized, and these + * must be reconfigured upon re-enabling. + */ + utrlba = hwq->req_queue_addr & 0xffffffff; + utrlbau = hwq->req_queue_addr >> 32; + ufshci_mmio_write_4(ctrlr, utrlba, utrlba); + ufshci_mmio_write_4(ctrlr, utrlbau, utrlbau); hcs = ufshci_mmio_read_4(ctrlr, hcs); if (!(hcs & UFSHCIM(UFSHCI_HCS_REG_UTRLRDY))) { ufshci_printf(ctrlr, "UTP transfer request list is not ready\n"); - return (ENXIO); + error = ENXIO; + goto out; } utrldbr = ufshci_mmio_read_4(ctrlr, utrldbr); @@ -434,7 +463,10 @@ ufshci_req_sdb_enable(struct ufshci_controller *ctrlr, hwq->recovery_state = RECOVERY_NONE; - return (0); +out: + mtx_unlock(&hwq->qlock); + mtx_unlock(&hwq->recovery_lock); + return (error); } int