git: 4dd9e4ed9771 - main - powerpc/booke(pmap): Flash-invalidate TLB on TID rollover

The branch main has been updated by jhibbits:

URL: https://cgit.FreeBSD.org/src/commit/?id=4dd9e4ed9771630388cdf49ba3bcd1a608b05c9c

commit 4dd9e4ed9771630388cdf49ba3bcd1a608b05c9c
Author:     Justin Hibbits <jhibbits@FreeBSD.org>
AuthorDate: 2026-07-05 23:05:13 +0000
Commit:     Justin Hibbits <jhibbits@FreeBSD.org>
CommitDate: 2026-07-06 21:23:55 +0000

    powerpc/booke(pmap): Flash-invalidate TLB on TID rollover
    
    When the TID rolls over on a given CPU, simply flash-invalidate the
    TLB instead of walking the TLB to only invalidate the repurposed TID.
    Walking 256 entries is expensive, and we'll likely be inserting a bunch
    new ones anyway in the new environment, since 256 really only handles
    1MB of storage, so the likelihood of other mappings continuing to exist
    in the TLB when their thread owner is scheduled again is very very
    small.
---
 sys/powerpc/booke/pmap_32.c | 24 ++----------------------
 1 file changed, 2 insertions(+), 22 deletions(-)

diff --git a/sys/powerpc/booke/pmap_32.c b/sys/powerpc/booke/pmap_32.c
index 7d27d1fe407e..ef946194b649 100644
--- a/sys/powerpc/booke/pmap_32.c
+++ b/sys/powerpc/booke/pmap_32.c
@@ -939,8 +939,6 @@ static void
 tid_flush(tlbtid_t tid)
 {
 	register_t msr;
-	uint32_t mas0, mas1, mas2;
-	int entry, way;
 
 	/* Don't evict kernel translations */
 	if (tid == TID_KERNEL)
@@ -963,26 +961,8 @@ tid_flush(tlbtid_t tid)
 		__asm __volatile("wrtee %0" :: "r"(msr));
 		return;
 	}
+	/* Flash invalidate TLB0 instead of walking the TLB to invalidate. */
+	mtspr(SPR_MMUCSR0, MMUCSR0_L2TLB0_FI);
 
-	for (way = 0; way < TLB0_WAYS; way++)
-		for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) {
-			mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
-			mtspr(SPR_MAS0, mas0);
-
-			mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT;
-			mtspr(SPR_MAS2, mas2);
-
-			__asm __volatile("isync; tlbre");
-
-			mas1 = mfspr(SPR_MAS1);
-
-			if (!(mas1 & MAS1_VALID))
-				continue;
-			if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid)
-				continue;
-			mas1 &= ~MAS1_VALID;
-			mtspr(SPR_MAS1, mas1);
-			__asm __volatile("isync; tlbwe; isync; msync");
-		}
 	__asm __volatile("wrtee %0" :: "r"(msr));
 }