git: 96156003ec0c - main - aq(4): Style, whitespace and misc cleanup
- Go to: [ bottom of page ] [ top of archives ] [ this month ]
Date: Mon, 05 Jan 2026 17:15:23 UTC
The branch main has been updated by emaste:
URL: https://cgit.FreeBSD.org/src/commit/?id=96156003ec0c70de88a448d48d8e9bd37913589f
commit 96156003ec0c70de88a448d48d8e9bd37913589f
Author: Ed Maste <emaste@FreeBSD.org>
AuthorDate: 2025-11-19 15:34:25 +0000
Commit: Ed Maste <emaste@FreeBSD.org>
CommitDate: 2026-01-05 17:15:06 +0000
aq(4): Style, whitespace and misc cleanup
The compiled objects do not change other than a few diagnostic messages
that include __LINE__.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D54304
---
sys/dev/aq/aq_common.h | 26 +-
sys/dev/aq/aq_dbg.c | 97 +-
sys/dev/aq/aq_dbg.h | 38 +-
sys/dev/aq/aq_device.h | 60 +-
sys/dev/aq/aq_fw.c | 504 +++++-----
sys/dev/aq/aq_fw.h | 35 +-
sys/dev/aq/aq_fw1x.c | 399 ++++----
sys/dev/aq/aq_fw2x.c | 600 +++++------
sys/dev/aq/aq_hw.c | 1085 ++++++++++----------
sys/dev/aq/aq_hw.h | 242 ++---
sys/dev/aq/aq_hw_llh.c | 2120 ++++++++++++++++++++-------------------
sys/dev/aq/aq_hw_llh.h | 873 ++++++++--------
sys/dev/aq/aq_hw_llh_internal.h | 2 +-
sys/dev/aq/aq_irq.c | 94 +-
sys/dev/aq/aq_main.c | 478 +++++----
sys/dev/aq/aq_media.c | 56 +-
sys/dev/aq/aq_ring.c | 286 +++---
sys/dev/aq/aq_ring.h | 190 ++--
18 files changed, 3721 insertions(+), 3464 deletions(-)
diff --git a/sys/dev/aq/aq_common.h b/sys/dev/aq/aq_common.h
index 5f52ce915bc5..af59ecf7af1e 100644
--- a/sys/dev/aq/aq_common.h
+++ b/sys/dev/aq/aq_common.h
@@ -37,14 +37,6 @@
#include <sys/types.h>
-#define s8 __int8_t
-#define u8 __uint8_t
-#define u16 __uint16_t
-#define s16 __int16_t
-#define u32 __uint32_t
-#define u64 __uint64_t
-#define s64 __int64_t
-#define s32 int
#define ETIME ETIMEDOUT
#define EOK 0
@@ -59,18 +51,18 @@
#endif
#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \
- do { \
+do { \
unsigned int i; \
- for (i = _N_; (!(_B_)) && i; --i) { \
- usec_delay(_US_); \
- } \
- if (!i) { \
- err = -1; \
- } \
- } while (0)
+ for (i = _N_; (!(_B_)) && i; --i) { \
+ usec_delay(_US_); \
+ } \
+ if (!i) { \
+ err = -1; \
+ } \
+} while (0)
-#define LOWORD(a) ((u16)(a))
+#define LOWORD(a) ((uint16_t)(a))
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define AQ_VER "0.0.5"
diff --git a/sys/dev/aq/aq_dbg.c b/sys/dev/aq/aq_dbg.c
index 5340fc46a223..495991fafbdc 100644
--- a/sys/dev/aq/aq_dbg.c
+++ b/sys/dev/aq/aq_dbg.c
@@ -46,7 +46,7 @@ __FBSDID("$FreeBSD$");
const aq_debug_level dbg_level_ = lvl_detail;
-const u32 dbg_categories_ = dbg_init | dbg_config | dbg_fw;
+const uint32_t dbg_categories_ = dbg_init | dbg_config | dbg_fw;
@@ -55,24 +55,25 @@ const u32 dbg_categories_ = dbg_init | dbg_config | dbg_fw;
(BIT(BIT_BEGIN - BIT_END + 1) -1))
#define __field(TYPE, VAR) TYPE VAR;
-void trace_aq_tx_descr(int ring_idx, unsigned int pointer, volatile u64 descr[2])
+void
+trace_aq_tx_descr(int ring_idx, unsigned int pointer, volatile uint64_t descr[2])
{
#if AQ_CFG_DEBUG_LVL > 2
struct __entry{
__field(unsigned int, ring_idx)
__field(unsigned int, pointer)
/* Tx Descriptor */
- __field(u64, data_buf_addr)
- __field(u32, pay_len)
- __field(u8, ct_en)
- __field(u8, ct_idx)
- __field(u16, rsvd2)
- __field(u8, tx_cmd)
- __field(u8, eop)
- __field(u8, dd)
- __field(u16, buf_len)
- __field(u8, rsvd1)
- __field(u8, des_typ)
+ __field(uint64_t, data_buf_addr)
+ __field(uint32_t, pay_len)
+ __field(uint8_t, ct_en)
+ __field(uint8_t, ct_idx)
+ __field(uint16_t, rsvd2)
+ __field(uint8_t, tx_cmd)
+ __field(uint8_t, eop)
+ __field(uint8_t, dd)
+ __field(uint16_t, buf_len)
+ __field(uint8_t, rsvd1)
+ __field(uint8_t, des_typ)
} entry;
entry.ring_idx = ring_idx;
@@ -98,27 +99,28 @@ void trace_aq_tx_descr(int ring_idx, unsigned int pointer, volatile u64 descr[2]
#endif
}
-void trace_aq_rx_descr(int ring_idx, unsigned int pointer, volatile u64 descr[2])
+void
+trace_aq_rx_descr(int ring_idx, unsigned int pointer, volatile uint64_t descr[2])
{
#if AQ_CFG_DEBUG_LVL > 2
- u8 dd;
- u8 eop;
- u8 rx_stat;
- u8 rx_estat;
- u8 rsc_cnt;
- u16 pkt_len;
- u16 next_desp;
- u16 vlan_tag;
-
- u8 rss_type;
- u8 pkt_type;
- u8 rdm_err;
- u8 avb_ts;
- u8 rsvd;
- u8 rx_cntl;
- u8 sph;
- u16 hdr_len;
- u32 rss_hash;
+ uint8_t dd;
+ uint8_t eop;
+ uint8_t rx_stat;
+ uint8_t rx_estat;
+ uint8_t rsc_cnt;
+ uint16_t pkt_len;
+ uint16_t next_desp;
+ uint16_t vlan_tag;
+
+ uint8_t rss_type;
+ uint8_t pkt_type;
+ uint8_t rdm_err;
+ uint8_t avb_ts;
+ uint8_t rsvd;
+ uint8_t rx_cntl;
+ uint8_t sph;
+ uint16_t hdr_len;
+ uint32_t rss_hash;
rss_hash = DESCR_FIELD(descr[0], 63, 32);
hdr_len = DESCR_FIELD(descr[0], 31, 22);
@@ -149,24 +151,26 @@ void trace_aq_rx_descr(int ring_idx, unsigned int pointer, volatile u64 descr[2]
#endif
}
-void trace_aq_tx_context_descr(int ring_idx, unsigned int pointer, volatile u64 descr[2])
+void
+trace_aq_tx_context_descr(int ring_idx, unsigned int pointer,
+ volatile uint64_t descr[2])
{
#if AQ_CFG_DEBUG_LVL > 2
struct __entry_s{
__field(unsigned int, ring_idx)
__field(unsigned int, pointer)
/* Tx Context Descriptor */
- __field(u16, out_len)
- __field(u8, tun_len)
- __field(u64, resvd3)
- __field(u16, mss_len)
- __field(u8, l4_len)
- __field(u8, l3_len)
- __field(u8, l2_len)
- __field(u8, ct_cmd)
- __field(u16, vlan_tag)
- __field(u8, ct_idx)
- __field(u8, des_typ)
+ __field(uint16_t, out_len)
+ __field(uint8_t, tun_len)
+ __field(uint64_t, resvd3)
+ __field(uint16_t, mss_len)
+ __field(uint8_t, l4_len)
+ __field(uint8_t, l3_len)
+ __field(uint8_t, l2_len)
+ __field(uint8_t, ct_cmd)
+ __field(uint16_t, vlan_tag)
+ __field(uint8_t, ct_idx)
+ __field(uint8_t, des_typ)
} entry;
struct __entry_s *__entry = &entry;
__entry->ring_idx = ring_idx;
@@ -192,7 +196,8 @@ void trace_aq_tx_context_descr(int ring_idx, unsigned int pointer, volatile u64
#endif
}
-void DumpHex(const void* data, size_t size) {
+void
+DumpHex(const void* data, size_t size) {
#if AQ_CFG_DEBUG_LVL > 3
char ascii[17];
size_t i, j;
@@ -234,4 +239,4 @@ void DumpHex(const void* data, size_t size) {
}
}
#endif
-}
\ No newline at end of file
+}
diff --git a/sys/dev/aq/aq_dbg.h b/sys/dev/aq/aq_dbg.h
index 8d02f483b2f7..d90a8599e085 100644
--- a/sys/dev/aq/aq_dbg.h
+++ b/sys/dev/aq/aq_dbg.h
@@ -38,8 +38,8 @@
#ifndef AQ_DBG_H
#define AQ_DBG_H
-#include <sys/syslog.h>
#include <sys/systm.h>
+#include <sys/syslog.h>
/*
Debug levels:
0 - no debug
@@ -78,10 +78,10 @@ Debug levels:
#if AQ_CFG_DEBUG_LVL > 2
#define AQ_DBG_DUMP_DESC(desc) { \
- volatile u8 *raw = (volatile u8*)(desc); \
- printf( "07-00 %02X%02X%02X%02X %02X%02X%02X%02X 15-08 %02X%02X%02X%02X %02X%02X%02X%02X\n", \
- raw[7], raw[6], raw[5], raw[4], raw[3], raw[2], raw[1], raw[0], \
- raw[15], raw[14], raw[13], raw[12], raw[11], raw[10], raw[9], raw[8]); \
+ volatile uint8_t *raw = (volatile uint8_t*)(desc); \
+ printf( "07-00 %02X%02X%02X%02X %02X%02X%02X%02X 15-08 %02X%02X%02X%02X %02X%02X%02X%02X\n", \
+ raw[7], raw[6], raw[5], raw[4], raw[3], raw[2], raw[1], raw[0], \
+ raw[15], raw[14], raw[13], raw[12], raw[11], raw[10], raw[9], raw[8]); \
}\
#else
@@ -90,27 +90,27 @@ Debug levels:
typedef enum aq_debug_level
{
- lvl_error = LOG_ERR,
- lvl_warn = LOG_WARNING,
- lvl_trace = LOG_NOTICE,
- lvl_detail = LOG_INFO,
+ lvl_error = LOG_ERR,
+ lvl_warn = LOG_WARNING,
+ lvl_trace = LOG_NOTICE,
+ lvl_detail = LOG_INFO,
} aq_debug_level;
typedef enum aq_debug_category
{
- dbg_init = 1,
- dbg_config = 1 << 1,
- dbg_tx = 1 << 2,
- dbg_rx = 1 << 3,
- dbg_intr = 1 << 4,
- dbg_fw = 1 << 5,
+ dbg_init = 1,
+ dbg_config = 1 << 1,
+ dbg_tx = 1 << 2,
+ dbg_rx = 1 << 3,
+ dbg_intr = 1 << 4,
+ dbg_fw = 1 << 5,
} aq_debug_category;
#define __FILENAME__ (__builtin_strrchr(__FILE__, '/') ? __builtin_strrchr(__FILE__, '/') + 1 : __FILE__)
extern const aq_debug_level dbg_level_;
-extern const u32 dbg_categories_;
+extern const uint32_t dbg_categories_;
#define log_base_(_lvl, _fmt, args...) printf( "atlantic: " _fmt "\n", ##args)
@@ -130,9 +130,9 @@ extern const u32 dbg_categories_;
#define trace(_cat, _fmt, args...) trace_base_(lvl_trace, _cat, _fmt, ##args)
#define trace_detail(_cat, _fmt, args...) trace_base_(lvl_detail, _cat, _fmt, ##args)
-void trace_aq_tx_descr(int ring_idx, unsigned int pointer, volatile u64 descr[2]);
-void trace_aq_rx_descr(int ring_idx, unsigned int pointer, volatile u64 descr[2]);
-void trace_aq_tx_context_descr(int ring_idx, unsigned int pointer, volatile u64 descr[2]);
+void trace_aq_tx_descr(int ring_idx, unsigned int pointer, volatile uint64_t descr[2]);
+void trace_aq_rx_descr(int ring_idx, unsigned int pointer, volatile uint64_t descr[2]);
+void trace_aq_tx_context_descr(int ring_idx, unsigned int pointer, volatile uint64_t descr[2]);
void DumpHex(const void* data, size_t size);
#endif // AQ_DBG_H
diff --git a/sys/dev/aq/aq_device.h b/sys/dev/aq/aq_device.h
index 2c0d8df77cb9..2b170f710840 100644
--- a/sys/dev/aq/aq_device.h
+++ b/sys/dev/aq/aq_device.h
@@ -54,40 +54,40 @@ enum aq_media_type {
AQ_LINK_10G )
struct aq_stats_s {
- u64 prc;
- u64 uprc;
- u64 mprc;
- u64 bprc;
- u64 cprc;
- u64 erpr;
- u64 dpc;
- u64 brc;
- u64 ubrc;
- u64 mbrc;
- u64 bbrc;
-
- u64 ptc;
- u64 uptc;
- u64 mptc;
- u64 bptc;
- u64 erpt;
- u64 btc;
- u64 ubtc;
- u64 mbtc;
- u64 bbtc;
+ uint64_t prc;
+ uint64_t uprc;
+ uint64_t mprc;
+ uint64_t bprc;
+ uint64_t cprc;
+ uint64_t erpr;
+ uint64_t dpc;
+ uint64_t brc;
+ uint64_t ubrc;
+ uint64_t mbrc;
+ uint64_t bbrc;
+
+ uint64_t ptc;
+ uint64_t uptc;
+ uint64_t mptc;
+ uint64_t bptc;
+ uint64_t erpt;
+ uint64_t btc;
+ uint64_t ubtc;
+ uint64_t mbtc;
+ uint64_t bbtc;
};
enum aq_dev_state_e {
- AQ_DEV_STATE_UNLOAD,
- AQ_DEV_STATE_PCI_STOP,
- AQ_DEV_STATE_DOWN,
- AQ_DEV_STATE_UP,
+ AQ_DEV_STATE_UNLOAD,
+ AQ_DEV_STATE_PCI_STOP,
+ AQ_DEV_STATE_DOWN,
+ AQ_DEV_STATE_UP,
};
struct aq_rx_filters {
- unsigned int rule_cnt;
- struct aq_rx_filter_vlan vlan_filters[AQ_HW_VLAN_MAX_FILTERS];
- struct aq_rx_filter_l2 etype_filters[AQ_HW_ETYPE_MAX_FILTERS];
+ unsigned int rule_cnt;
+ struct aq_rx_filter_vlan vlan_filters[AQ_HW_VLAN_MAX_FILTERS];
+ struct aq_rx_filter_l2 etype_filters[AQ_HW_ETYPE_MAX_FILTERS];
};
struct aq_vlan_tag {
@@ -102,7 +102,7 @@ struct aq_dev {
if_shared_ctx_t sctx;
struct ifmedia * media;
- struct aq_hw hw;
+ struct aq_hw hw;
enum aq_media_type media_type;
uint32_t link_speeds;
@@ -142,7 +142,7 @@ int aq_update_hw_stats(aq_dev_t *aq_dev);
void aq_initmedia(aq_dev_t *aq_dev);
int aq_linkstat_isr(void *arg);
int aq_isr_rx(void *arg);
-void aq_mediastatus_update(aq_dev_t *aq_dev, u32 link_speed, const struct aq_hw_fc_info *fc_neg);
+void aq_mediastatus_update(aq_dev_t *aq_dev, uint32_t link_speed, const struct aq_hw_fc_info *fc_neg);
void aq_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
int aq_mediachange(struct ifnet *ifp);
void aq_if_update_admin_status(if_ctx_t ctx);
diff --git a/sys/dev/aq/aq_fw.c b/sys/dev/aq/aq_fw.c
index 3596074dbafc..fac720ba2327 100644
--- a/sys/dev/aq/aq_fw.c
+++ b/sys/dev/aq/aq_fw.c
@@ -55,10 +55,10 @@ __FBSDID("$FreeBSD$");
typedef enum aq_fw_bootloader_mode
{
- boot_mode_unknown = 0,
- boot_mode_flb,
- boot_mode_rbl_flash,
- boot_mode_rbl_host_bootload,
+ boot_mode_unknown = 0,
+ boot_mode_flb,
+ boot_mode_rbl_flash,
+ boot_mode_rbl_host_bootload,
} aq_fw_bootloader_mode;
#define AQ_CFG_HOST_BOOT_DISABLE 0
@@ -67,22 +67,22 @@ typedef enum aq_fw_bootloader_mode
#define MAC_FW_START_TIMEOUT_MS 10000
#define FW_LOADER_START_TIMEOUT_MS 10000
-const u32 NO_RESET_SCRATCHPAD_ADDRESS = 0;
-const u32 NO_RESET_SCRATCHPAD_LEN_RES = 1;
-const u32 NO_RESET_SCRATCHPAD_RBL_STATUS = 2;
-const u32 NO_RESET_SCRATCHPAD_RBL_STATUS_2 = 3;
-const u32 WRITE_DATA_COMPLETE = 0x55555555;
-const u32 WRITE_DATA_CHUNK_DONE = 0xaaaaaaaa;
-const u32 WRITE_DATA_FAIL_WRONG_ADDRESS = 0x66666666;
+const uint32_t NO_RESET_SCRATCHPAD_ADDRESS = 0;
+const uint32_t NO_RESET_SCRATCHPAD_LEN_RES = 1;
+const uint32_t NO_RESET_SCRATCHPAD_RBL_STATUS = 2;
+const uint32_t NO_RESET_SCRATCHPAD_RBL_STATUS_2 = 3;
+const uint32_t WRITE_DATA_COMPLETE = 0x55555555;
+const uint32_t WRITE_DATA_CHUNK_DONE = 0xaaaaaaaa;
+const uint32_t WRITE_DATA_FAIL_WRONG_ADDRESS = 0x66666666;
-const u32 WAIT_WRITE_TIMEOUT = 1;
-const u32 WAIT_WRITE_TIMEOUT_COUNT = 1000;
+const uint32_t WAIT_WRITE_TIMEOUT = 1;
+const uint32_t WAIT_WRITE_TIMEOUT_COUNT = 1000;
-const u32 RBL_STATUS_SUCCESS = 0xabba;
-const u32 RBL_STATUS_FAILURE = 0xbad;
-const u32 RBL_STATUS_HOST_BOOT = 0xf1a7;
+const uint32_t RBL_STATUS_SUCCESS = 0xabba;
+const uint32_t RBL_STATUS_FAILURE = 0xbad;
+const uint32_t RBL_STATUS_HOST_BOOT = 0xf1a7;
-const u32 SCRATCHPAD_FW_LOADER_STATUS = (0x40 / sizeof(u32));
+const uint32_t SCRATCHPAD_FW_LOADER_STATUS = (0x40 / sizeof(uint32_t));
extern struct aq_firmware_ops aq_fw1x_ops;
@@ -95,258 +95,268 @@ int mac_soft_reset_rbl_(struct aq_hw* hw, aq_fw_bootloader_mode* mode);
int wait_init_mac_firmware_(struct aq_hw* hw);
-int aq_fw_reset(struct aq_hw* hw)
+int
+aq_fw_reset(struct aq_hw* hw)
{
- int ver = AQ_READ_REG(hw, 0x18);
- u32 bootExitCode = 0;
- int k;
-
- for (k = 0; k < 1000; ++k) {
- u32 flbStatus = reg_glb_daisy_chain_status1_get(hw);
- bootExitCode = AQ_READ_REG(hw, 0x388);
- if (flbStatus != 0x06000000 || bootExitCode != 0)
- break;
- }
-
- if (k == 1000) {
- aq_log_error("Neither RBL nor FLB started");
- return (-EBUSY);
- }
-
- hw->rbl_enabled = bootExitCode != 0;
-
- trace(dbg_init, "RBL enabled = %d", hw->rbl_enabled);
-
- /* Having FW version 0 is an indicator that cold start
- * is in progress. This means two things:
- * 1) Driver have to wait for FW/HW to finish boot (500ms giveup)
- * 2) Driver may skip reset sequence and save time.
- */
- if (hw->fast_start_enabled && !ver) {
- int err = wait_init_mac_firmware_(hw);
- /* Skip reset as it just completed */
- if (!err)
- return (0);
- }
-
- aq_fw_bootloader_mode mode = boot_mode_unknown;
- int err = mac_soft_reset_(hw, &mode);
- if (err < 0) {
- aq_log_error("MAC reset failed: %d", err);
- return (err);
- }
-
- switch (mode) {
- case boot_mode_flb:
- aq_log("FLB> F/W successfully loaded from flash.");
- hw->flash_present = true;
- return wait_init_mac_firmware_(hw);
-
- case boot_mode_rbl_flash:
- aq_log("RBL> F/W loaded from flash. Host Bootload disabled.");
- hw->flash_present = true;
- return wait_init_mac_firmware_(hw);
-
- case boot_mode_unknown:
- aq_log_error("F/W bootload error: unknown bootloader type");
- return (-ENOTSUP);
-
- case boot_mode_rbl_host_bootload:
+ int ver = AQ_READ_REG(hw, 0x18);
+ uint32_t bootExitCode = 0;
+ int k;
+
+ for (k = 0; k < 1000; ++k) {
+ uint32_t flbStatus = reg_glb_daisy_chain_status1_get(hw);
+ bootExitCode = AQ_READ_REG(hw, 0x388);
+ if (flbStatus != 0x06000000 || bootExitCode != 0)
+ break;
+ }
+
+ if (k == 1000) {
+ aq_log_error("Neither RBL nor FLB started");
+ return (-EBUSY);
+ }
+
+ hw->rbl_enabled = bootExitCode != 0;
+
+ trace(dbg_init, "RBL enabled = %d", hw->rbl_enabled);
+
+ /* Having FW version 0 is an indicator that cold start
+ * is in progress. This means two things:
+ * 1) Driver have to wait for FW/HW to finish boot (500ms giveup)
+ * 2) Driver may skip reset sequence and save time.
+ */
+ if (hw->fast_start_enabled && !ver) {
+ int err = wait_init_mac_firmware_(hw);
+ /* Skip reset as it just completed */
+ if (!err)
+ return (0);
+ }
+
+ aq_fw_bootloader_mode mode = boot_mode_unknown;
+ int err = mac_soft_reset_(hw, &mode);
+ if (err < 0) {
+ aq_log_error("MAC reset failed: %d", err);
+ return (err);
+ }
+
+ switch (mode) {
+ case boot_mode_flb:
+ aq_log("FLB> F/W successfully loaded from flash.");
+ hw->flash_present = true;
+ return wait_init_mac_firmware_(hw);
+
+ case boot_mode_rbl_flash:
+ aq_log("RBL> F/W loaded from flash. Host Bootload disabled.");
+ hw->flash_present = true;
+ return wait_init_mac_firmware_(hw);
+
+ case boot_mode_unknown:
+ aq_log_error("F/W bootload error: unknown bootloader type");
+ return (-ENOTSUP);
+
+ case boot_mode_rbl_host_bootload:
#if AQ_CFG_HOST_BOOT_DISABLE
- aq_log_error("RBL> Host Bootload mode: this driver does not support Host Boot");
- return (-ENOTSUP);
+ aq_log_error("RBL> Host Bootload mode: this driver does not support Host Boot");
+ return (-ENOTSUP);
#else
- trace(dbg_init, "RBL> Host Bootload mode");
- break;
+ trace(dbg_init, "RBL> Host Bootload mode");
+ break;
#endif // HOST_BOOT_DISABLE
- }
+ }
- /*
- * #todo: Host Boot
- */
- aq_log_error("RBL> F/W Host Bootload not implemented");
+ /*
+ * #todo: Host Boot
+ */
+ aq_log_error("RBL> F/W Host Bootload not implemented");
- return (-ENOTSUP);
+ return (-ENOTSUP);
}
-int aq_fw_ops_init(struct aq_hw* hw)
+int
+aq_fw_ops_init(struct aq_hw* hw)
{
- if (hw->fw_version.raw == 0)
- hw->fw_version.raw = AQ_READ_REG(hw, 0x18);
-
- aq_log("MAC F/W version is %d.%d.%d",
- hw->fw_version.major_version, hw->fw_version.minor_version,
- hw->fw_version.build_number);
-
- if (hw->fw_version.major_version == 1) {
- trace(dbg_init, "using F/W ops v1.x");
- hw->fw_ops = &aq_fw1x_ops;
- return (EOK);
- } else if (hw->fw_version.major_version >= 2) {
- trace(dbg_init, "using F/W ops v2.x");
- hw->fw_ops = &aq_fw2x_ops;
- return (EOK);
- }
-
- aq_log_error("aq_fw_ops_init(): invalid F/W version %#x", hw->fw_version.raw);
- return (-ENOTSUP);
+ if (hw->fw_version.raw == 0)
+ hw->fw_version.raw = AQ_READ_REG(hw, 0x18);
+
+ aq_log("MAC F/W version is %d.%d.%d",
+ hw->fw_version.major_version, hw->fw_version.minor_version,
+ hw->fw_version.build_number);
+
+ if (hw->fw_version.major_version == 1) {
+ trace(dbg_init, "using F/W ops v1.x");
+ hw->fw_ops = &aq_fw1x_ops;
+ return (EOK);
+ } else if (hw->fw_version.major_version >= 2) {
+ trace(dbg_init, "using F/W ops v2.x");
+ hw->fw_ops = &aq_fw2x_ops;
+ return (EOK);
+ }
+
+ aq_log_error("aq_fw_ops_init(): invalid F/W version %#x",
+ hw->fw_version.raw);
+ return (-ENOTSUP);
}
-int mac_soft_reset_(struct aq_hw* hw, aq_fw_bootloader_mode* mode /*= nullptr*/)
+int
+mac_soft_reset_(struct aq_hw* hw, aq_fw_bootloader_mode* mode /*= nullptr*/)
{
- if (hw->rbl_enabled) {
- return mac_soft_reset_rbl_(hw, mode);
- } else {
- if (mode)
- *mode = boot_mode_flb;
-
- return mac_soft_reset_flb_(hw);
- }
+ if (hw->rbl_enabled) {
+ return mac_soft_reset_rbl_(hw, mode);
+ } else {
+ if (mode)
+ *mode = boot_mode_flb;
+
+ return mac_soft_reset_flb_(hw);
+ }
}
-int mac_soft_reset_flb_(struct aq_hw* hw)
+int
+mac_soft_reset_flb_(struct aq_hw* hw)
{
- int k;
-
- reg_global_ctl2_set(hw, 0x40e1);
- // Let Felicity hardware to complete SMBUS transaction before Global software reset.
- msec_delay(50);
-
- /*
- * If SPI burst transaction was interrupted(before running the script), global software
- * reset may not clear SPI interface. Clean it up manually before global reset.
- */
- reg_glb_nvr_provisioning2_set(hw, 0xa0);
- reg_glb_nvr_interface1_set(hw, 0x9f);
- reg_glb_nvr_interface1_set(hw, 0x809f);
- msec_delay(50);
-
- reg_glb_standard_ctl1_set(hw, (reg_glb_standard_ctl1_get(hw) & ~glb_reg_res_dis_msk) | glb_soft_res_msk);
-
- // Kickstart.
- reg_global_ctl2_set(hw, 0x80e0);
- reg_mif_power_gating_enable_control_set(hw, 0);
- if (!hw->fast_start_enabled)
- reg_glb_general_provisioning9_set(hw, 1);
-
- /*
- * For the case SPI burst transaction was interrupted (by MCP reset above),
- * wait until it is completed by hardware.
- */
- msec_delay(50); // Sleep for 10 ms.
-
- /* MAC Kickstart */
- if (!hw->fast_start_enabled) {
- reg_global_ctl2_set(hw, 0x180e0);
-
- u32 flb_status = 0;
- int k;
- for (k = 0; k < 1000; ++k) {
- flb_status = reg_glb_daisy_chain_status1_get(hw) & 0x10;
- if (flb_status != 0)
- break;
- msec_delay(10); // Sleep for 10 ms.
- }
-
- if (flb_status == 0) {
- trace_error(dbg_init, "FLB> MAC kickstart failed: timed out");
- return (false);
- }
-
- trace(dbg_init, "FLB> MAC kickstart done, %d ms", k);
- /* FW reset */
- reg_global_ctl2_set(hw, 0x80e0);
- // Let Felicity hardware complete SMBUS transaction before Global software reset.
- msec_delay(50);
- }
- reg_glb_cpu_sem_set(hw, 1, 0);
-
- // PHY Kickstart: #undone
-
- // Global software reset
- rx_rx_reg_res_dis_set(hw, 0);
- tx_tx_reg_res_dis_set(hw, 0);
- mpi_tx_reg_res_dis_set(hw, 0);
- reg_glb_standard_ctl1_set(hw, (reg_glb_standard_ctl1_get(hw) & ~glb_reg_res_dis_msk) | glb_soft_res_msk);
-
- bool restart_completed = false;
- for (k = 0; k < 1000; ++k) {
- restart_completed = reg_glb_fw_image_id1_get(hw) != 0;
- if (restart_completed)
- break;
- msec_delay(10);
- }
-
- if (!restart_completed) {
- trace_error(dbg_init, "FLB> Global Soft Reset failed");
- return (false);
- }
-
- trace(dbg_init, "FLB> F/W restart: %d ms", k * 10);
- return (true);
+ int k;
+
+ reg_global_ctl2_set(hw, 0x40e1);
+ // Let Felicity hardware to complete SMBUS transaction before Global software reset.
+ msec_delay(50);
+
+ /*
+ * If SPI burst transaction was interrupted(before running the script), global software
+ * reset may not clear SPI interface. Clean it up manually before global reset.
+ */
+ reg_glb_nvr_provisioning2_set(hw, 0xa0);
+ reg_glb_nvr_interface1_set(hw, 0x9f);
+ reg_glb_nvr_interface1_set(hw, 0x809f);
+ msec_delay(50);
+
+ reg_glb_standard_ctl1_set(hw, (reg_glb_standard_ctl1_get(hw) & ~glb_reg_res_dis_msk) | glb_soft_res_msk);
+
+ // Kickstart.
+ reg_global_ctl2_set(hw, 0x80e0);
+ reg_mif_power_gating_enable_control_set(hw, 0);
+ if (!hw->fast_start_enabled)
+ reg_glb_general_provisioning9_set(hw, 1);
+
+ /*
+ * For the case SPI burst transaction was interrupted (by MCP reset above),
+ * wait until it is completed by hardware.
+ */
+ msec_delay(50); // Sleep for 10 ms.
+
+ /* MAC Kickstart */
+ if (!hw->fast_start_enabled) {
+ reg_global_ctl2_set(hw, 0x180e0);
+
+ uint32_t flb_status = 0;
+ int k;
+ for (k = 0; k < 1000; ++k) {
+ flb_status = reg_glb_daisy_chain_status1_get(hw) & 0x10;
+ if (flb_status != 0)
+ break;
+ msec_delay(10); // Sleep for 10 ms.
+ }
+
+ if (flb_status == 0) {
+ trace_error(dbg_init,
+ "FLB> MAC kickstart failed: timed out");
+ return (false);
+ }
+
+ trace(dbg_init, "FLB> MAC kickstart done, %d ms", k);
+ /* FW reset */
+ reg_global_ctl2_set(hw, 0x80e0);
+ // Let Felicity hardware complete SMBUS transaction before Global software reset.
+ msec_delay(50);
+ }
+ reg_glb_cpu_sem_set(hw, 1, 0);
+
+ // PHY Kickstart: #undone
+
+ // Global software reset
+ rx_rx_reg_res_dis_set(hw, 0);
+ tx_tx_reg_res_dis_set(hw, 0);
+ mpi_tx_reg_res_dis_set(hw, 0);
+ reg_glb_standard_ctl1_set(hw, (reg_glb_standard_ctl1_get(hw) & ~glb_reg_res_dis_msk) | glb_soft_res_msk);
+
+ bool restart_completed = false;
+ for (k = 0; k < 1000; ++k) {
+ restart_completed = reg_glb_fw_image_id1_get(hw) != 0;
+ if (restart_completed)
+ break;
+ msec_delay(10);
+ }
+
+ if (!restart_completed) {
+ trace_error(dbg_init, "FLB> Global Soft Reset failed");
+ return (false);
+ }
+
+ trace(dbg_init, "FLB> F/W restart: %d ms", k * 10);
+ return (true);
}
-int mac_soft_reset_rbl_(struct aq_hw* hw, aq_fw_bootloader_mode* mode)
+int
+mac_soft_reset_rbl_(struct aq_hw* hw, aq_fw_bootloader_mode* mode)
{
- trace(dbg_init, "RBL> MAC reset STARTED!");
-
- reg_global_ctl2_set(hw, 0x40e1);
- reg_glb_cpu_sem_set(hw, 1, 0);
- reg_mif_power_gating_enable_control_set(hw, 0);
-
- // MAC FW will reload PHY FW if 1E.1000.3 was cleaned - #undone
-
- reg_glb_cpu_no_reset_scratchpad_set(hw, 0xDEAD, NO_RESET_SCRATCHPAD_RBL_STATUS);
-
- // Global software reset
- rx_rx_reg_res_dis_set(hw, 0);
- tx_tx_reg_res_dis_set(hw, 0);
- mpi_tx_reg_res_dis_set(hw, 0);
- reg_glb_standard_ctl1_set(hw, (reg_glb_standard_ctl1_get(hw) & ~glb_reg_res_dis_msk) | glb_soft_res_msk);
-
- reg_global_ctl2_set(hw, 0x40e0);
-
- // Wait for RBL to finish boot process.
- u16 rbl_status = 0;
- for (int k = 0; k < RBL_TIMEOUT_MS; ++k) {
- rbl_status = LOWORD(reg_glb_cpu_no_reset_scratchpad_get(hw, NO_RESET_SCRATCHPAD_RBL_STATUS));
- if (rbl_status != 0 && rbl_status != 0xDEAD)
- break;
-
- msec_delay(1);
- }
-
- if (rbl_status == 0 || rbl_status == 0xDEAD) {
- trace_error(dbg_init, "RBL> RBL restart failed: timeout");
- return (-EBUSY);
- }
-
- if (rbl_status == RBL_STATUS_SUCCESS) {
- if (mode)
- *mode = boot_mode_rbl_flash;
- trace(dbg_init, "RBL> reset complete! [Flash]");
- } else if (rbl_status == RBL_STATUS_HOST_BOOT) {
- if (mode)
- *mode = boot_mode_rbl_host_bootload;
- trace(dbg_init, "RBL> reset complete! [Host Bootload]");
- } else {
- trace_error(dbg_init, "unknown RBL status 0x%x", rbl_status);
- return (-EBUSY);
- }
-
- return (EOK);
+ trace(dbg_init, "RBL> MAC reset STARTED!");
+
+ reg_global_ctl2_set(hw, 0x40e1);
+ reg_glb_cpu_sem_set(hw, 1, 0);
+ reg_mif_power_gating_enable_control_set(hw, 0);
+
+ // MAC FW will reload PHY FW if 1E.1000.3 was cleaned - #undone
+
+ reg_glb_cpu_no_reset_scratchpad_set(hw, 0xDEAD,
+ NO_RESET_SCRATCHPAD_RBL_STATUS);
+
+ // Global software reset
+ rx_rx_reg_res_dis_set(hw, 0);
+ tx_tx_reg_res_dis_set(hw, 0);
+ mpi_tx_reg_res_dis_set(hw, 0);
+ reg_glb_standard_ctl1_set(hw, (reg_glb_standard_ctl1_get(hw) & ~glb_reg_res_dis_msk) | glb_soft_res_msk);
+
+ reg_global_ctl2_set(hw, 0x40e0);
+
+ // Wait for RBL to finish boot process.
+ uint16_t rbl_status = 0;
+ for (int k = 0; k < RBL_TIMEOUT_MS; ++k) {
+ rbl_status = LOWORD(reg_glb_cpu_no_reset_scratchpad_get(hw, NO_RESET_SCRATCHPAD_RBL_STATUS));
+ if (rbl_status != 0 && rbl_status != 0xDEAD)
+ break;
+
+ msec_delay(1);
+ }
+
+ if (rbl_status == 0 || rbl_status == 0xDEAD) {
+ trace_error(dbg_init, "RBL> RBL restart failed: timeout");
+ return (-EBUSY);
+ }
+
+ if (rbl_status == RBL_STATUS_SUCCESS) {
+ if (mode)
+ *mode = boot_mode_rbl_flash;
+ trace(dbg_init, "RBL> reset complete! [Flash]");
+ } else if (rbl_status == RBL_STATUS_HOST_BOOT) {
+ if (mode)
+ *mode = boot_mode_rbl_host_bootload;
+ trace(dbg_init, "RBL> reset complete! [Host Bootload]");
+ } else {
+ trace_error(dbg_init, "unknown RBL status 0x%x", rbl_status);
+ return (-EBUSY);
+ }
+
+ return (EOK);
}
-int wait_init_mac_firmware_(struct aq_hw* hw)
+int
+wait_init_mac_firmware_(struct aq_hw* hw)
{
- for (int i = 0; i < MAC_FW_START_TIMEOUT_MS; ++i) {
- if ((hw->fw_version.raw = AQ_READ_REG(hw, 0x18)) != 0)
- return (EOK);
+ for (int i = 0; i < MAC_FW_START_TIMEOUT_MS; ++i) {
+ if ((hw->fw_version.raw = AQ_READ_REG(hw, 0x18)) != 0)
+ return (EOK);
- msec_delay(1);
- }
+ msec_delay(1);
+ }
- trace_error(dbg_init, "timeout waiting for reg 0x18. MAC f/w NOT READY");
- return (-EBUSY);
+ trace_error(dbg_init,
+ "timeout waiting for reg 0x18. MAC f/w NOT READY");
+ return (-EBUSY);
}
diff --git a/sys/dev/aq/aq_fw.h b/sys/dev/aq/aq_fw.h
index 7ffb60b29421..ea2c37b6c92c 100644
--- a/sys/dev/aq/aq_fw.h
+++ b/sys/dev/aq/aq_fw.h
@@ -38,35 +38,36 @@ struct aq_hw;
typedef enum aq_fw_link_speed
{
- aq_fw_none = 0,
- aq_fw_100M = (1 << 0),
- aq_fw_1G = (1 << 1),
- aq_fw_2G5 = (1 << 2),
- aq_fw_5G = (1 << 3),
- aq_fw_10G = (1 << 4),
+ aq_fw_none = 0,
+ aq_fw_100M = (1 << 0),
+ aq_fw_1G = (1 << 1),
+ aq_fw_2G5 = (1 << 2),
+ aq_fw_5G = (1 << 3),
+ aq_fw_10G = (1 << 4),
} aq_fw_link_speed_t;
*** 9485 LINES SKIPPED ***