git: 178d0b5b8da7 - main - libpmc: Import AMD Zen 6 PMU events.
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Date: Fri, 27 Feb 2026 22:08:49 UTC
The branch main has been updated by imp:
URL: https://cgit.FreeBSD.org/src/commit/?id=178d0b5b8da7480f455273aedf40dd8f1e785d3f
commit 178d0b5b8da7480f455273aedf40dd8f1e785d3f
Author: Ali Mashtizadeh <mashti@uwaterloo.ca>
AuthorDate: 2026-02-24 15:52:00 +0000
Commit: Warner Losh <imp@FreeBSD.org>
CommitDate: 2026-02-27 21:27:35 +0000
libpmc: Import AMD Zen 6 PMU events.
Sponsored by: Netflix
Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/2049
---
.../arch/x86/amdzen6/branch-prediction.json | 93 ++
lib/libpmc/pmu-events/arch/x86/amdzen6/decode.json | 139 +++
.../pmu-events/arch/x86/amdzen6/execution.json | 192 ++++
.../arch/x86/amdzen6/floating-point.json | 1106 ++++++++++++++++++++
.../pmu-events/arch/x86/amdzen6/inst-cache.json | 120 +++
.../pmu-events/arch/x86/amdzen6/l2-cache.json | 326 ++++++
.../pmu-events/arch/x86/amdzen6/l3-cache.json | 177 ++++
.../pmu-events/arch/x86/amdzen6/load-store.json | 523 +++++++++
.../arch/x86/amdzen6/memory-controller.json | 101 ++
.../pmu-events/arch/x86/amdzen6/pipeline.json | 99 ++
.../pmu-events/arch/x86/amdzen6/recommended.json | 339 ++++++
lib/libpmc/pmu-events/arch/x86/mapfile.csv | 3 +-
12 files changed, 3217 insertions(+), 1 deletion(-)
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen6/branch-prediction.json b/lib/libpmc/pmu-events/arch/x86/amdzen6/branch-prediction.json
new file mode 100644
index 000000000000..dd70069f68ed
--- /dev/null
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen6/branch-prediction.json
@@ -0,0 +1,93 @@
+[
+ {
+ "EventName": "bp_l1_tlb_miss_l2_tlb_hit",
+ "EventCode": "0x84",
+ "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
+ },
+ {
+ "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
+ "EventCode": "0x85",
+ "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 4k pages.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
+ "EventCode": "0x85",
+ "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 2M pages.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
+ "EventCode": "0x85",
+ "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 1G pages.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
+ "EventCode": "0x85",
+ "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for coalesced pages (16k pages created from four adjacent 4k pages).",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
+ "EventCode": "0x85",
+ "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for all page sizes.",
+ "UMask": "0x0f"
+ },
+ {
+ "EventName": "bp_pipe_correct",
+ "EventCode": "0x8b",
+ "BriefDescription": "Branch predictor pipeline flushes due to internal conditions such as a second level prediction structure."
+ },
+ {
+ "EventName": "bp_var_target_pred",
+ "EventCode": "0x8e",
+ "BriefDescription": "Indirect predictions (branch used the indirect predictor to make a prediction)."
+ },
+ {
+ "EventName": "bp_early_redir",
+ "EventCode": "0x91",
+ "BriefDescription": "Early redirects sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected."
+ },
+ {
+ "EventName": "bp_l1_tlb_fetch_hit.if4k",
+ "EventCode": "0x94",
+ "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages (16k pages created from four adjacent 4k pages).",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "bp_l1_tlb_fetch_hit.if2m",
+ "EventCode": "0x94",
+ "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "bp_l1_tlb_fetch_hit.if1g",
+ "EventCode": "0x94",
+ "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "bp_l1_tlb_fetch_hit.all",
+ "EventCode": "0x94",
+ "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
+ "UMask": "0x07"
+ },
+ {
+ "EventName": "bp_fe_redir.resync",
+ "EventCode": "0x9f",
+ "BriefDescription": "Redirects of the pipeline frontend caused by resyncs. These are retire time pipeline restarts.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "bp_fe_redir.ex_redir",
+ "EventCode": "0x9f",
+ "BriefDescription": "Redirects of the pipeline frontend caused by mispredicts. These are used for branch direction correction and handling indirect branch target mispredicts.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "bp_fe_redir.all",
+ "EventCode": "0x9f",
+ "BriefDescription": "Redirects of the pipeline frontend caused by any reason."
+ }
+]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen6/decode.json b/lib/libpmc/pmu-events/arch/x86/amdzen6/decode.json
new file mode 100644
index 000000000000..c5d37fbac948
--- /dev/null
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen6/decode.json
@@ -0,0 +1,139 @@
+[
+ {
+ "EventName": "de_op_queue_empty",
+ "EventCode": "0xa9",
+ "BriefDescription": "Cycles where the op queue is empty. Such cycles indicate that the frontend is not delivering instructions fast enough."
+ },
+ {
+ "EventName": "de_src_op_disp.x86_decoder",
+ "EventCode": "0xaa",
+ "BriefDescription": "Ops dispatched from x86 decoder.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "de_src_op_disp.op_cache",
+ "EventCode": "0xaa",
+ "BriefDescription": "Ops dispatched from op cache.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "de_src_op_disp.all",
+ "EventCode": "0xaa",
+ "BriefDescription": "Ops dispatched from any source.",
+ "UMask": "0x07"
+ },
+ {
+ "EventName": "de_dis_ops_from_decoder.any_fp",
+ "EventCode": "0xab",
+ "BriefDescription": "Ops dispatched from the decoder to a floating-point unit.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "de_dis_ops_from_decoder.any_int",
+ "EventCode": "0xab",
+ "BriefDescription": "Ops dispatched from the decoder to an integer unit.",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "de_disp_stall_cycles_dynamic_tokens_part1.int_phy_reg_file_rsrc_stall",
+ "EventCode": "0xae",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to integer physical register file resource stalls.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.load_queue_rsrc_stall",
+ "EventCode": "0xae",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to load queue token stalls.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.store_queue_rsrc_stall",
+ "EventCode": "0xae",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to store queue token stalls.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.taken_brnch_buffer_rsrc",
+ "EventCode": "0xae",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to taken branch buffer resource stalls.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.fp_sch_rsrc_stall",
+ "EventCode": "0xae",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to floating-point non-schedulable queue token stalls.",
+ "UMask": "0x40"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq0",
+ "EventCode": "0xaf",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 0 tokens.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq1",
+ "EventCode": "0xaf",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 1 tokens.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq2",
+ "EventCode": "0xaf",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 2 tokens.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq3",
+ "EventCode": "0xaf",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 3 tokens.",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq4",
+ "EventCode": "0xaf",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 4 tokens.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq5",
+ "EventCode": "0xaf",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 5 tokens.",
+ "UMask": "0x20"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.ret_q",
+ "EventCode": "0xaf",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of retire queue tokens.",
+ "UMask": "0x80"
+ },
+ {
+ "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.all",
+ "EventCode": "0xaf",
+ "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to any token stalls.",
+ "UMask": "0xbf"
+ },
+ {
+ "EventName": "de_no_dispatch_per_slot.no_ops_from_frontend",
+ "EventCode": "0x1a0",
+ "BriefDescription": "Dispatch slots in each cycle that were empty because the frontend did not supply ops.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "de_no_dispatch_per_slot.backend_stalls",
+ "EventCode": "0x1a0",
+ "BriefDescription": "Dispatch slots in each cycle that were unused because of backend stalls.",
+ "UMask": "0x1e"
+ },
+ {
+ "EventName": "de_no_dispatch_per_slot.smt_contention",
+ "EventCode": "0x1a0",
+ "BriefDescription": "Dispatch slots in each cycle that were unused because the dispatch cycle was granted to the other SMT thread.",
+ "UMask": "0x60"
+ },
+ {
+ "EventName": "de_additional_resource_stalls.dispatch_stalls",
+ "EventCode": "0x1a2",
+ "BriefDescription": "Counts additional cycles where dispatch is stalled due to a lack of dispatch resources.",
+ "UMask": "0x30"
+ }
+]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen6/execution.json b/lib/libpmc/pmu-events/arch/x86/amdzen6/execution.json
new file mode 100644
index 000000000000..1b80acc89b6f
--- /dev/null
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen6/execution.json
@@ -0,0 +1,192 @@
+[
+ {
+ "EventName": "ex_ret_instr",
+ "EventCode": "0xc0",
+ "BriefDescription": "Retired instructions."
+ },
+ {
+ "EventName": "ex_ret_ops",
+ "EventCode": "0xc1",
+ "BriefDescription": "Retired macro-ops."
+ },
+ {
+ "EventName": "ex_ret_brn",
+ "EventCode": "0xc2",
+ "BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
+ },
+ {
+ "EventName": "ex_ret_brn_misp",
+ "EventCode": "0xc3",
+ "BriefDescription": "Retired branch instructions that were mispredicted."
+ },
+ {
+ "EventName": "ex_ret_brn_tkn",
+ "EventCode": "0xc4",
+ "BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
+ },
+ {
+ "EventName": "ex_ret_brn_tkn_misp",
+ "EventCode": "0xc5",
+ "BriefDescription": "Retired taken branch instructions that were mispredicted."
+ },
+ {
+ "EventName": "ex_ret_brn_far",
+ "EventCode": "0xc6",
+ "BriefDescription": "Retired far control transfers (far call, far jump, far return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
+ },
+ {
+ "EventName": "ex_ret_near_ret",
+ "EventCode": "0xc8",
+ "BriefDescription": "Retired near returns (RET or RET Iw)."
+ },
+ {
+ "EventName": "ex_ret_near_ret_mispred",
+ "EventCode": "0xc9",
+ "BriefDescription": "Retired near returns that were mispredicted. Each misprediction incurs the same penalty as that of a mispredicted conditional branch instruction."
+ },
+ {
+ "EventName": "ex_ret_brn_ind_misp",
+ "EventCode": "0xca",
+ "BriefDescription": "Retired indirect branch instructions that were mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as that of a mispredicted conditional branch instruction."
+ },
+ {
+ "EventName": "ex_ret_brn_ind",
+ "EventCode": "0xcc",
+ "BriefDescription": "Retired indirect branch instructions."
+ },
+ {
+ "EventName": "ex_ret_brn_cond",
+ "EventCode": "0xd1",
+ "BriefDescription": "Retired conditional branch instructions."
+ },
+ {
+ "EventName": "ex_div_busy",
+ "EventCode": "0xd3",
+ "BriefDescription": "Cycles where the divider is busy."
+ },
+ {
+ "EventName": "ex_div_count",
+ "EventCode": "0xd4",
+ "BriefDescription": "Divide ops executed."
+ },
+ {
+ "EventName": "ex_no_retire.empty",
+ "EventCode": "0xd6",
+ "BriefDescription": "Cycles where the thread does not retire any ops due to a lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "ex_no_retire.not_complete",
+ "EventCode": "0xd6",
+ "BriefDescription": "Cycles where the thread does not retire any ops as the oldest retire slot is waiting to be marked as completed.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "ex_no_retire.other",
+ "EventCode": "0xd6",
+ "BriefDescription": "Cycles where the thread does not retire any ops due to other reasons (retire breaks, traps, faults, etc.).",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "ex_no_retire.thread_not_selected",
+ "EventCode": "0xd6",
+ "BriefDescription": "Cycles where the thread does not retire any ops as thread arbitration did not select the current thread.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "ex_no_retire.load_not_complete",
+ "EventCode": "0xd6",
+ "BriefDescription": "Cycles where the thread does not retire any ops due to missing load completion.",
+ "UMask": "0xa2"
+ },
+ {
+ "EventName": "ex_ret_ucode_instr",
+ "EventCode": "0x1c1",
+ "BriefDescription": "Retired microcoded instructions."
+ },
+ {
+ "EventName": "ex_ret_ucode_ops",
+ "EventCode": "0x1c2",
+ "BriefDescription": "Retired microcode ops."
+ },
+ {
+ "EventName": "ex_ret_brn_cond_misp",
+ "EventCode": "0x1c7",
+ "BriefDescription": "Retired conditional branch instructions that were mispredicted due to direction mismatch."
+ },
+ {
+ "EventName": "ex_ret_brn_uncond_ind_near_misp",
+ "EventCode": "0x1c8",
+ "BriefDescription": "Retired unconditional indirect near branch instructions that were mispredicted."
+ },
+ {
+ "EventName": "ex_ret_brn_uncond",
+ "EventCode": "0x1c9",
+ "BriefDescription": "Retired unconditional branch instructions."
+ },
+ {
+ "EventName": "ex_tagged_ibs_ops.tagged",
+ "EventCode": "0x1cf",
+ "BriefDescription": "Execution IBS tagged ops.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "ex_tagged_ibs_ops.tagged_ret",
+ "EventCode": "0x1cf",
+ "BriefDescription": "Execution IBS tagged ops that retired.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "ex_tagged_ibs_ops.rollovers",
+ "EventCode": "0x1cf",
+ "BriefDescription": "Execution IBS periodic counter rollovers due to a previous tagged op not being IBS complete.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "ex_tagged_ibs_ops.filtered",
+ "EventCode": "0x1cf",
+ "BriefDescription": "Execution IBS tagged ops that retired but were discarded due to IBS filtering.",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "ex_tagged_ibs_ops.valid",
+ "EventCode": "0x1cf",
+ "BriefDescription": "Execution IBS tagged ops that resulted in a valid sample and an IBS interrupt.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "ex_ret_fused_instr",
+ "EventCode": "0x1d0",
+ "BriefDescription": "Retired fused instructions."
+ },
+ {
+ "EventName": "ex_mprof_ibs_ops.tagged",
+ "EventCode": "0x2c0",
+ "BriefDescription": "Memory Profiler IBS tagged ops.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "ex_mprof_ibs_ops.tagged_ret",
+ "EventCode": "0x2c0",
+ "BriefDescription": "Memory Profiler IBS tagged ops that retired.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "ex_mprof_ibs_ops.rollovers",
+ "EventCode": "0x2c0",
+ "BriefDescription": "Memory Profiler IBS periodic counter rollovers due to a previous tagged op not being IBS complete.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "ex_mprof_ibs_ops.filtered",
+ "EventCode": "0x2c0",
+ "BriefDescription": "Memory Profiler IBS tagged ops that retired but were discarded due to IBS filtering.",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "ex_mprof_ibs_ops.valid",
+ "EventCode": "0x2c0",
+ "BriefDescription": "Memory Profiler IBS tagged ops that resulted in a valid sample and an IBS interrupt.",
+ "UMask": "0x10"
+ }
+]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen6/floating-point.json b/lib/libpmc/pmu-events/arch/x86/amdzen6/floating-point.json
new file mode 100644
index 000000000000..03cb039434de
--- /dev/null
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen6/floating-point.json
@@ -0,0 +1,1106 @@
+[
+ {
+ "EventName": "fp_ret_x87_fp_ops.add_sub_ops",
+ "EventCode": "0x02",
+ "BriefDescription": "Retired x87 floating-point add and subtract uops.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "fp_ret_x87_fp_ops.mul_ops",
+ "EventCode": "0x02",
+ "BriefDescription": "Retired x87 floating-point multiply uops.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "fp_ret_x87_fp_ops.div_sqrt_ops",
+ "EventCode": "0x02",
+ "BriefDescription": "Retired x87 floating-point divide and square root uops.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "fp_ret_x87_fp_ops.all",
+ "EventCode": "0x02",
+ "BriefDescription": "Retired x87 floating-point uops of all types.",
+ "UMask": "0x07"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.add_sub_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX add and subtract FLOPs.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.mult_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX multiply FLOPs.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.div_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX divide and square root FLOPs.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.mac_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX multiply-accumulate FLOPs (each operation is counted as 2 FLOPs, bfloat operations are not included).",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.bfloat16_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX bfloat16 FLOPs.",
+ "UMask": "0x20"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.scalar_single_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX scalar single-precision (FP32) FLOPs.",
+ "UMask": "0x40"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.packed_single_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX packed single-precision (FP32) FLOPs.",
+ "UMask": "0x60"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.scalar_double_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX scalar double-precision (FP64) FLOPs.",
+ "UMask": "0x80"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.packed_double_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX packed double-precision (FP64) FLOPs.",
+ "UMask": "0xa0"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.scalar_half_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX scalar half-precision (FP16) FLOPs.",
+ "UMask": "0xa0"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.packed_half_flops",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX packed half-precision (FP16) FLOPs.",
+ "UMask": "0xa0"
+ },
+ {
+ "EventName": "fp_ret_sse_avx_ops.all",
+ "EventCode": "0x03",
+ "BriefDescription": "Retired SSE and AVX FLOPs of all types.",
+ "UMask": "0x0f"
+ },
+ {
+ "EventName": "fp_ops_ret_by_width.x87",
+ "EventCode": "0x08",
+ "BriefDescription": "Retired x87 floating-point uops.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "fp_ops_ret_by_width.mmx",
+ "EventCode": "0x08",
+ "BriefDescription": "Retired MMX floating-point uops.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "fp_ops_ret_by_width.scalar",
+ "EventCode": "0x08",
+ "BriefDescription": "Retired scalar floating-point uops.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "fp_ops_ret_by_width.pack_128",
+ "EventCode": "0x08",
+ "BriefDescription": "Retired packed 128-bit floating-point uops.",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "fp_ops_ret_by_width.pack_256",
+ "EventCode": "0x08",
+ "BriefDescription": "Retired packed 256-bit floating-point uops.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "fp_ops_ret_by_width.pack_512",
+ "EventCode": "0x08",
+ "BriefDescription": "Retired packed 512-bit floating-point uops.",
+ "UMask": "0x20"
+ },
+ {
+ "EventName": "fp_ops_ret_by_width.all",
+ "EventCode": "0x08",
+ "BriefDescription": "Retired floating-point uops of all widths.",
+ "UMask": "0x3f"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_add",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point add uops.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_sub",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point subtract uops.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_mul",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point multiply uops.",
+ "UMask": "0x03"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_mac",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point multiply-accumulate uops.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_div",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point divide uops.",
+ "UMask": "0x05"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_sqrt",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point square root uops.",
+ "UMask": "0x06"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_cmp",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point compare uops.",
+ "UMask": "0x07"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_cvt",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point convert uops.",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_blend",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point blend uops.",
+ "UMask": "0x09"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_move",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point move uops.",
+ "UMask": "0x0a"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_shuffle",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+ "UMask": "0x0b"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_bfloat",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point bfloat uops.",
+ "UMask": "0x0c"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_logical",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point move uops.",
+ "UMask": "0x0d"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_other",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point uops of other types.",
+ "UMask": "0x0e"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.scalar_all",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired scalar floating-point uops of all types.",
+ "UMask": "0x0f"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_add",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point add uops.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_sub",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point subtract uops.",
+ "UMask": "0x20"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_mul",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point multiply uops.",
+ "UMask": "0x30"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_mac",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point multiply-accumulate uops.",
+ "UMask": "0x40"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_div",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point divide uops.",
+ "UMask": "0x50"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_sqrt",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point square root uops.",
+ "UMask": "0x60"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_cmp",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point compare uops.",
+ "UMask": "0x70"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_cvt",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point convert uops.",
+ "UMask": "0x80"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_blend",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point blend uops.",
+ "UMask": "0x90"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_move",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point move uops.",
+ "UMask": "0xa0"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_shuffle",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+ "UMask": "0xb0"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_bfloat",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point bfloat uops.",
+ "UMask": "0xc0"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_logical",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point logical uops.",
+ "UMask": "0xd0"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_other",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point uops of other types.",
+ "UMask": "0xe0"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.vector_all",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired vector floating-point uops of all types.",
+ "UMask": "0xf0"
+ },
+ {
+ "EventName": "fp_ops_ret_by_type.all",
+ "EventCode": "0x0a",
+ "BriefDescription": "Retired floating-point uops of all types.",
+ "UMask": "0xff"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_add",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer add uops.",
+ "UMask": "0x01"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_sub",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer subtract uops.",
+ "UMask": "0x02"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_mul",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer multiply uops.",
+ "UMask": "0x03"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_mac",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer multiply-accumulate uops.",
+ "UMask": "0x04"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_aes",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer AES uops.",
+ "UMask": "0x05"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_sha",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer SHA uops.",
+ "UMask": "0x06"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_cmp",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer compare uops.",
+ "UMask": "0x07"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_cvt",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer convert or pack uops.",
+ "UMask": "0x08"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_shift",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer shift or rotate uops.",
+ "UMask": "0x09"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_mov",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer move uops.",
+ "UMask": "0x0a"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_shuffle",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+ "UMask": "0x0b"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_vnni",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer VNNI uops.",
+ "UMask": "0x0c"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_logical",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer logical uops.",
+ "UMask": "0x0d"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_other",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer multiply uops of other types.",
+ "UMask": "0x0e"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.mmx_all",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired MMX integer uops of all types.",
+ "UMask": "0x0f"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_add",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer add uops.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_sub",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer subtract uops.",
+ "UMask": "0x20"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_mul",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer multiply uops.",
+ "UMask": "0x30"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_mac",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer multiply-accumulate uops.",
+ "UMask": "0x40"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_aes",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer AES uops.",
+ "UMask": "0x50"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_sha",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer SHA uops.",
+ "UMask": "0x60"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_cmp",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer compare uops.",
+ "UMask": "0x70"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_cvt",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer convert or pack uops.",
+ "UMask": "0x80"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_shift",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer shift or rotate uops.",
+ "UMask": "0x90"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_mov",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer move uops.",
+ "UMask": "0xa0"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_shuffle",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+ "UMask": "0xb0"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_vnni",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer VNNI uops.",
+ "UMask": "0xc0"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_logical",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer logical uops.",
+ "UMask": "0xd0"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_other",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer uops of other types.",
+ "UMask": "0xe0"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.sse_avx_all",
+ "EventCode": "0x0b",
+ "BriefDescription": "Retired SSE and AVX integer uops of all types.",
+ "UMask": "0xf0"
+ },
+ {
+ "EventName": "fp_sse_avx_ops_ret.all",
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