git: bfbcd310bd49 - main - Revert "sym(4): Employ memory barriers also on x86"

The branch main has been updated by marius:

URL: https://cgit.FreeBSD.org/src/commit/?id=bfbcd310bd4997c4ddb21bb81d61f2f29c68937c

commit bfbcd310bd4997c4ddb21bb81d61f2f29c68937c
Author:     Marius Strobl <marius@FreeBSD.org>
AuthorDate: 2026-01-28 21:20:42 +0000
Commit:     Marius Strobl <marius@FreeBSD.org>
CommitDate: 2026-02-02 21:53:13 +0000

    Revert "sym(4): Employ memory barriers also on x86"
    
    The problem will be avoided in a different way.
    
    This reverts commit e769bc77184312b6137a9b180c97b87c0760b849.
---
 sys/dev/sym/sym_hipd.c | 42 +++++++++++++++++++++++++++---------------
 1 file changed, 27 insertions(+), 15 deletions(-)

diff --git a/sys/dev/sym/sym_hipd.c b/sys/dev/sym/sym_hipd.c
index f78d595a73ce..0e51607fb07a 100644
--- a/sys/dev/sym/sym_hipd.c
+++ b/sys/dev/sym/sym_hipd.c
@@ -58,6 +58,7 @@
  */
 
 #include <sys/cdefs.h>
+#define SYM_DRIVER_NAME	"sym-1.6.5-20000902"
 
 /* #define SYM_DEBUG_GENERIC_SUPPORT */
 
@@ -113,16 +114,27 @@ typedef	u_int32_t u32;
 #include <dev/sym/sym_fw.h>
 
 /*
- *  Architectures may implement weak ordering that requires memory barriers
- *  to be used for LOADS and STORES to become globally visible (and also IO
- *  barriers when they make sense).
- */
-#ifdef __powerpc__
-#define	MEMORY_READ_BARRIER()	__asm__ volatile("eieio; sync" : : : "memory")
-#define	MEMORY_WRITE_BARRIER()	MEMORY_READ_BARRIER()
+ *  IA32 architecture does not reorder STORES and prevents
+ *  LOADS from passing STORES. It is called `program order'
+ *  by Intel and allows device drivers to deal with memory
+ *  ordering by only ensuring that the code is not reordered
+ *  by the compiler when ordering is required.
+ *  Other architectures implement a weaker ordering that
+ *  requires memory barriers (and also IO barriers when they
+ *  make sense) to be used.
+ */
+#if	defined	__i386__ || defined __amd64__
+#define MEMORY_BARRIER()	do { ; } while(0)
+#elif	defined	__powerpc__
+#define MEMORY_BARRIER()	__asm__ volatile("eieio; sync" : : : "memory")
+#elif	defined	__arm__
+#define MEMORY_BARRIER()	dmb()
+#elif	defined	__aarch64__
+#define MEMORY_BARRIER()	dmb(sy)
+#elif	defined __riscv
+#define MEMORY_BARRIER()	fence()
 #else
-#define	MEMORY_READ_BARRIER()	rmb()
-#define	MEMORY_WRITE_BARRIER()	wmb()
+#error	"Not supported platform"
 #endif
 
 /*
@@ -880,13 +892,13 @@ struct sym_nvram {
  */
 #define OUTL_DSP(v)				\
 	do {					\
-		MEMORY_WRITE_BARRIER();		\
+		MEMORY_BARRIER();		\
 		OUTL (nc_dsp, (v));		\
 	} while (0)
 
 #define OUTONB_STD()				\
 	do {					\
-		MEMORY_WRITE_BARRIER();		\
+		MEMORY_BARRIER();		\
 		OUTONB (nc_dcntl, (STD|NOCOM));	\
 	} while (0)
 
@@ -2896,7 +2908,7 @@ static void sym_put_start_queue(hcb_p np, ccb_p cp)
 	if (qidx >= MAX_QUEUE*2) qidx = 0;
 
 	np->squeue [qidx]	   = cpu_to_scr(np->idletask_ba);
-	MEMORY_WRITE_BARRIER();
+	MEMORY_BARRIER();
 	np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba);
 
 	np->squeueput = qidx;
@@ -2908,7 +2920,7 @@ static void sym_put_start_queue(hcb_p np, ccb_p cp)
 	 *  Script processor may be waiting for reselect.
 	 *  Wake it up.
 	 */
-	MEMORY_WRITE_BARRIER();
+	MEMORY_BARRIER();
 	OUTB (nc_istat, SIGP|np->istat_sem);
 }
 
@@ -3049,7 +3061,7 @@ static int sym_wakeup_done (hcb_p np)
 
 		cp = sym_ccb_from_dsa(np, dsa);
 		if (cp) {
-			MEMORY_READ_BARRIER();
+			MEMORY_BARRIER();
 			sym_complete_ok (np, cp);
 			++n;
 		} else
@@ -3847,7 +3859,7 @@ static void sym_intr1 (hcb_p np)
 	 *  On paper, a memory barrier may be needed here.
 	 *  And since we are paranoid ... :)
 	 */
-	MEMORY_READ_BARRIER();
+	MEMORY_BARRIER();
 
 	/*
 	 *  First, interrupts we want to service cleanly.