From nobody Sun Aug 30 01:09:48 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4hXYv658y5z6ppZG for ; Sun, 30 Aug 2026 01:09:54 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4hXYv61NcJz3ngS for ; Sun, 30 Aug 2026 01:09:54 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1788052194; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=6+U+4yhePHclUkmp+iQ95U1FySI4bHhddA5xAi2CH88=; b=btIvYSVSUEpq4GpMq879S4z8+Fo5HtSXY87XdOT2YXP0pBxAEXppbyMuUYC6Fs2HX1Ri45 WBcpjKZVasHTCaFcoXAQ2RoN1i6/Zmcs5Ye36X8mQj0WqIK5z7RQ0FOT4P76amyXk7McLD tcn5G4fGUJA4s5KMWAjukE5jygUi2zatVTf5tT744tPcSk5OHeFmeIglhEEikArRY+0Uud Vn9Pch4CrGnjRfYm6o+sxNh8u8NzoktQ/FNODYFlGaAnxQ3wzsj6XBFxftZIM+DNEaKeEH xoWiQTfo+GCsbFLbH2XR8IJYQe/zfViHxA+HB4eMOvi3w15+qYN7tK+6hPdHIg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1788052194; a=rsa-sha256; cv=none; b=ZhNwgwxgU7tQbXue+XgVRLkMdJIoBU2gSDUhVwRDKoG4E0A7GMmKzx7PEPnE/osjrYKZgR Ys2GkVaww5kj7pEWstM0sFkFUFlaak3/Wwt4TLnKfijtH1thQsSHD0d5VIOYfQPdyF19Wb K0oAZjoBBx/DfcBVAF6ai6huHFfYjDaPhhIcBZtBcvDNkpJJJ7igHY/kbDEIAOesiSe5ys PxnNYhy2iuAVdBr9B9MMZGk3KeTuTVvhrbCtlYRg6U/Z8N/bDleR+lLZT3tBSmf47kaEwD tSPWVX5mozgizDr5rMuWKJCit+896ETI/6mHFqQvgG53RjsyPbVK2E0abweXqQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1788052194; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=6+U+4yhePHclUkmp+iQ95U1FySI4bHhddA5xAi2CH88=; b=reX7L0CHhLFXzrM93W87nuhI+Qq7LBkkLJopuzCcl6RsC8qjCnpPtN+ewf2mF2UKuH63kw v7+V2k5aFZroYvicsgaQfBcGzQ3GEONlCoQxQjtesnMySQkKoUwK3b2Z36nd62c8uzmREt YM1FAxQj9oqdPAif59vGvN63dyF7sgwbQY6LwZGUuZFK1WJxv14czJE0AZSC+9s0grv/oT Mb/heC2kDeQ+DVBz83MmjItaYaPHlldw4SjmsdnrxLRRH6ZyQRVhDmrvOtIQCf/0CMbG67 DZxYfhKNgP4YV4tfuXVI0e0kFdaC00D2B7Dm2/my2EAd2zcQ67FTanLgiEzT1A== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4hXYv56k2tz13cD for ; Sun, 30 Aug 2026 01:09:53 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 3b92e by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Sun, 30 Aug 2026 01:09:48 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Kevin Bowling Subject: git: 02bf7486363c - stable/15 - e1000: Recover from PCH packet buffer ECC errors List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: kbowling X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: 02bf7486363c33a1a8b30c9e878df831a0613c4b Auto-Submitted: auto-generated Date: Sun, 30 Aug 2026 01:09:48 +0000 Message-Id: <6a9382dc.3b92e.2e5fcf6a@gitrepo.freebsd.org> The branch stable/15 has been updated by kbowling: URL: https://cgit.FreeBSD.org/src/commit/?id=02bf7486363c33a1a8b30c9e878df831a0613c4b commit 02bf7486363c33a1a8b30c9e878df831a0613c4b Author: Kevin Bowling AuthorDate: 2026-08-12 18:29:28 +0000 Commit: Kevin Bowling CommitDate: 2026-08-30 01:09:11 +0000 e1000: Recover from PCH packet buffer ECC errors PCH LAN controllers beginning with I217 report uncorrectable packet buffer ECC errors through ICR.ECCER. Descriptor memory errors stop the MAC and require a reset before traffic can resume. Enable the interrupt on the PCH generations whose shared code setup enables packet buffer ECC. Capture the read-clear PBECCSTS value in the interrupt filter, mask ECCER while recovery is pending, and request an iflib reset from the admin task. Reenable the cause only after hardware initialization succeeds. Hardware validation used an I219-LM and the documented ICS.ECCER bit to generate the fatal interrupt. This synthesizes the interrupt cause but does not corrupt packet buffer memory or alter its ECC byte counters. Three injections in one boot each requested one reset and recovered traffic without a panic or watchdog. IMS.ECCER and PBECCSTS.ECC_ENABLE remained set after every reset. MFC after: 2 weeks Sponsored by: BBOX.io (cherry picked from commit 39762c840a15e1b32b2e1acaca18d98c030f7c17) --- sys/dev/e1000/if_em.c | 104 +++++++++++++++++++++++++++++++++++++++++++++++--- sys/dev/e1000/if_em.h | 3 ++ 2 files changed, 102 insertions(+), 5 deletions(-) diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index bf3369a20bad..74ed1d985808 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -442,6 +442,9 @@ static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); +static void em_handle_fatal_error_intr(struct e1000_softc *, u32); +static bool em_handle_fatal_error_admin(struct e1000_softc *); +static void em_finish_fatal_error_reset(struct e1000_softc *); static void em_if_multi_set(if_ctx_t); static void em_if_update_admin_status(if_ctx_t); static void em_if_debug(if_ctx_t); @@ -485,6 +488,13 @@ static void em_disable_aspm(struct e1000_softc *); int em_intr(void *); +enum em_fatal_error_state { + EM_FATAL_ERROR_NONE, + EM_FATAL_ERROR_CAPTURING, + EM_FATAL_ERROR_DETECTED, + EM_FATAL_ERROR_RESET_REQUESTED, +}; + /* MSI-X handlers */ static int em_if_msix_intr_assign(if_ctx_t, int); static int em_msix_link(void *); @@ -1854,6 +1864,80 @@ em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, } } +static bool +em_has_pch_ecc(const struct e1000_hw *hw) +{ + + return (hw->mac.type >= e1000_pch_lpt && + hw->mac.type < e1000_82575); +} + +static u32 +em_fatal_error_intr_mask(struct e1000_softc *sc) +{ + + if (em_has_pch_ecc(&sc->hw) && + atomic_load_acq_32(&sc->fatal_error_state) == + EM_FATAL_ERROR_NONE) + return (E1000_IMS_ECCER); + return (0); +} + +/* + * Descriptor-memory ECC errors stop the PCH MAC. Capture the read-clear + * status before handing recovery to the iflib admin task. + */ +static void +em_handle_fatal_error_intr(struct e1000_softc *sc, u32 icr) +{ + struct e1000_hw *hw; + + if (!em_has_pch_ecc(&sc->hw) || (icr & E1000_ICR_ECCER) == 0) + return; + + hw = &sc->hw; + E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_ECCER); + if (!atomic_cmpset_32(&sc->fatal_error_state, + EM_FATAL_ERROR_NONE, EM_FATAL_ERROR_CAPTURING)) + return; + + sc->fatal_error_pbeccsts = E1000_READ_REG(hw, E1000_PBECCSTS); + atomic_store_rel_32(&sc->fatal_error_state, + EM_FATAL_ERROR_DETECTED); + iflib_admin_intr_deferred(sc->ctx); +} + +static bool +em_handle_fatal_error_admin(struct e1000_softc *sc) +{ + + if (!atomic_cmpset_acq_32(&sc->fatal_error_state, + EM_FATAL_ERROR_DETECTED, EM_FATAL_ERROR_RESET_REQUESTED)) + return (atomic_load_acq_32(&sc->fatal_error_state) != + EM_FATAL_ERROR_NONE); + + device_printf(sc->dev, + "uncorrectable packet-buffer ECC error: PBECCSTS %#x; " + "requesting reset\n", sc->fatal_error_pbeccsts); + sc->fatal_error_reset_count++; + iflib_request_reset(sc->ctx); + /* Re-enter the admin task so it observes the reset request. */ + iflib_admin_intr_deferred(sc->ctx); + return (true); +} + +static void +em_finish_fatal_error_reset(struct e1000_softc *sc) +{ + + if (atomic_load_acq_32(&sc->fatal_error_state) == + EM_FATAL_ERROR_NONE) + return; + + sc->fatal_error_pbeccsts = 0; + atomic_store_rel_32(&sc->fatal_error_state, EM_FATAL_ERROR_NONE); +} + /********************************************************************* * * Fast Legacy/MSI Combined Interrupt Service routine @@ -1902,6 +1986,8 @@ em_intr(void *arg) if (reg_icr & E1000_ICR_RXO) sc->rx_overruns++; + em_handle_fatal_error_intr(sc, reg_icr); + if (hw->mac.type >= e1000_82540) em_newitr(sc, que, rxr); @@ -1987,10 +2073,12 @@ em_msix_link(void *arg) if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) em_handle_link(sc->ctx); + em_handle_fatal_error_intr(sc, reg_icr); /* Re-arm unconditionally */ if (sc->hw.mac.type >= igb_mac_min) { - E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); + E1000_WRITE_REG(&sc->hw, E1000_IMS, + E1000_IMS_LSC | em_fatal_error_intr_mask(sc)); E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); } else if (sc->hw.mac.type == e1000_82574) { E1000_WRITE_REG(&sc->hw, E1000_IMS, @@ -2003,7 +2091,8 @@ em_msix_link(void *arg) if (reg_icr) E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); } else - E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); + E1000_WRITE_REG(&sc->hw, E1000_IMS, + E1000_IMS_LSC | em_fatal_error_intr_mask(sc)); return (FILTER_HANDLED); } @@ -2260,6 +2349,8 @@ em_if_update_admin_status(if_ctx_t ctx) u32 link_check, thstat, ctrl; bool reset_requested = false; + if (em_handle_fatal_error_admin(sc)) + return; link_check = thstat = ctrl = 0; /* Get the cached link value or read phy for real */ switch (hw->phy.media_type) { @@ -3358,6 +3449,7 @@ em_reset(if_ctx_t ctx) device_printf(dev, "Hardware Initialization Failed\n"); return; } + em_finish_fatal_error_reset(sc); if (hw->mac.type >= igb_mac_min) igb_init_dmac(sc, pba); @@ -4442,7 +4534,7 @@ em_if_intr_enable(if_ctx_t ctx) { struct e1000_softc *sc = iflib_get_softc(ctx); struct e1000_hw *hw = &sc->hw; - u32 ims_mask = IMS_ENABLE_MASK; + u32 ims_mask = IMS_ENABLE_MASK | em_fatal_error_intr_mask(sc); if (sc->intr_type == IFLIB_INTR_MSIX) { E1000_WRITE_REG(hw, EM_EIAC, sc->ims); @@ -4477,9 +4569,11 @@ igb_if_intr_enable(if_ctx_t ctx) E1000_WRITE_REG(hw, E1000_EIAC, mask); E1000_WRITE_REG(hw, E1000_EIAM, mask); E1000_WRITE_REG(hw, E1000_EIMS, mask); - E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); + E1000_WRITE_REG(hw, E1000_IMS, + E1000_IMS_LSC | em_fatal_error_intr_mask(sc)); } else - E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); + E1000_WRITE_REG(hw, E1000_IMS, + IMS_ENABLE_MASK | em_fatal_error_intr_mask(sc)); E1000_WRITE_FLUSH(hw); } diff --git a/sys/dev/e1000/if_em.h b/sys/dev/e1000/if_em.h index 6237639bd5a5..47acdd9ed8d5 100644 --- a/sys/dev/e1000/if_em.h +++ b/sys/dev/e1000/if_em.h @@ -618,6 +618,9 @@ struct e1000_softc { u32 pba; int link_mask; int tso_automasked; + u32 fatal_error_state; + u32 fatal_error_pbeccsts; + u64 fatal_error_reset_count; u64 que_mask;