From nobody Sat Aug 22 00:28:01 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4hRdLT3XChz6pq1p for ; Sat, 22 Aug 2026 00:28:01 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4hRdLT1rkXz3GCv for ; Sat, 22 Aug 2026 00:28:01 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1787358481; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=iWBy8xtUO7tRewuekWsznfNcEbcFPFc1mxQyjHq1OpM=; b=RXDEqfW2lX7PHw+Xg6ykr6soBaQdcDPZGd6XPq4wQMl3PGVRtuBfofWMYtloy+Nw9Dc+7L IWi+85MF2xK7VaYiGXi28qmydM1vq8PQtavJb/1xvvylJCTQAfg/BME6YyjnNti3YiW79p 2Z7+rvo1QJ7mjT3jX0azj1UHa8kfQdphhj8YMJ6oQU9rPb1tV5DFIdZ/h4lr57AZMZrFVR w0Yqsu6VgowXXUsP8HxtyNj9PfSbUFOH589de7xjs5pvn6R3VGtxJ3syqhFdJqI7nHg8Il r/FadjXAua9QsKpRsE8ZDnGfkuIG7l9zUSZ2sDWD9QK6x+QlOcOzwygKgjYTNA== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1787358481; a=rsa-sha256; cv=none; b=s/drbpCeh84vTV9dr5kgWxKEW/+qGV4vBpx5vfvr3/8UnEgu2EKlGIfo8i9GJJ1AWk6KPP Df2pBr+8y2yElgHCD9tsMPJqgQhA1U9Qqq7vGZRU14Sp860bz8nfoE8Iu+zR7ciKjfyecK QbKCSAvIgatxiIWOrpZBO/MIkzjOI42HtDfR38+DiayBlId5Bq/a5sD0W32gqr4UCJ3X9c MsVOgBzeAU22l+PoffwcIVN8Jy3k5389gXkhVN4WC0DsHkiHq4ArhZIovqvwr/yylUIoCg cdVKL67gSO9m8vBbIBNmGF59W6Psj5IoOSx6i9j6DeDnc7iAakNTCuOOH6o6cw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1787358481; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=iWBy8xtUO7tRewuekWsznfNcEbcFPFc1mxQyjHq1OpM=; b=VFjOv10YKL7CWXhSzGe3YXtpUV5MaM46qNq9PmH8Cin2nbFUNj1qG5Lee4IJRDvA9lfBcs 8FdhBy1aahIhC6ylT11uzSN2PLsm3Pd5d9SfKjGsqhwpgufi8KQnVLoJhObelGSXj6AsIS 0qhBH/LprJF5DMaONRfzsjltFCut5nVmL790K5NGIrRIIdZ7buS8ndUL6DiVBddqETiQ3w 8X72p8jsyRCyuh5rtg5rqBZSvuZrHqZ8IuAek1FPo05+9kEwBeC9kO86d/E1mVoHI09aub O4HJO1p4ZK9tidvDYHl/+h2NgYi/dusSbPaQRqKx+da6ueDiQwTsySETZ0a0xg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4hRdLT0gKxzB5K for ; Sat, 22 Aug 2026 00:28:01 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 2245e by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Sat, 22 Aug 2026 00:28:01 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Kevin Bowling Subject: git: 59709be69b07 - stable/15 - e1000: Program Tx descriptor control by family List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: kbowling X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: 59709be69b0700e0e7e539a9aae8962712cba851 Auto-Submitted: auto-generated Date: Sat, 22 Aug 2026 00:28:01 +0000 Message-Id: <6a88ed11.2245e.2e0da139@gitrepo.freebsd.org> The branch stable/15 has been updated by kbowling: URL: https://cgit.FreeBSD.org/src/commit/?id=59709be69b0700e0e7e539a9aae8962712cba851 commit 59709be69b0700e0e7e539a9aae8962712cba851 Author: Kevin Bowling AuthorDate: 2026-08-08 11:48:43 +0000 Commit: Kevin Bowling CommitDate: 2026-08-22 00:27:29 +0000 e1000: Program Tx descriptor control by family TXDCTL programming is family dependent. 82543 erratum 35 and 82544 erratum 20 require WTHRESH to remain zero; a nonzero value can corrupt descriptor writebacks and hang the controller. Leave all descriptor-control thresholds at their reset values on 82542, 82543, and 82544. On the remaining em controllers, retain the established PTHRESH=31, HTHRESH=1, WTHRESH=1, and descriptor granularity policy. Several legacy specification updates identify full descriptor writeback as a workaround for transmit descriptor-queue errata. TXDCTL bit 22 is also family dependent. It is COUNT_DESC on the 82571 family and 80003ES2LAN. Intel shared initialization explicitly sets raw bit 22 on both transmit queues of every supported ICH/PCH generation, although the integrated public documentation marks it reserved. Preserve that required setting when iflib programs the thresholds, as DPDK does. Clearing it caused a persistent I219 transmit stall under descriptor pressure. The combined em/igb setup also wrote LWTHRESH=1 on every em controller. The driver does not enable the TXD_LOW interrupt controlled by that field. Enumerate every supported em MAC type and leave the unused low-water threshold disabled. This keeps the legacy descriptor-writeback safety policies separate from igb sparse-RS operation while programming only the fields appropriate to each family. (cherry picked from commit 66baeec9f8a4c4b1609d255b62e3572e0618747f) --- sys/dev/e1000/if_em.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++----- sys/dev/e1000/if_em.h | 3 ++ 2 files changed, 78 insertions(+), 8 deletions(-) diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index 1e027861a175..b9a4ceb8d6a8 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -3686,6 +3686,74 @@ em_if_queues_free(if_ctx_t ctx) } } +static u32 +em_legacy_txdctl(struct e1000_hw *hw) +{ + u32 txdctl; + + /* + * Start with the established full-descriptor writeback policy. + * Several generations have descriptor-queue errata for which it is + * a documented workaround. The unsafe early controllers are + * overridden below. + */ + txdctl = EM_TX_PTHRESH | (EM_TX_HTHRESH << 8) | + (EM_TX_WTHRESH << 16) | E1000_TXDCTL_GRAN; + + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + case e1000_82573: + case e1000_82574: + case e1000_82583: + case e1000_80003es2lan: + /* Match the Intel shared-code policy for these families. */ + txdctl |= E1000_TXDCTL_COUNT_DESC; + break; + case e1000_ich8lan: + case e1000_ich9lan: + case e1000_ich10lan: + case e1000_pchlan: + case e1000_pch2lan: + case e1000_pch_lpt: + case e1000_pch_spt: + case e1000_pch_cnp: + case e1000_pch_tgp: + case e1000_pch_adp: + case e1000_pch_mtp: + case e1000_pch_ptp: + /* Preserve the required bit set by the integrated shared code. */ + txdctl |= (1U << 22); + break; + case e1000_82542: + case e1000_82543: + case e1000_82544: + /* + * 82543 erratum 35 and 82544 erratum 20 require + * WTHRESH=0. Leave all descriptor-control thresholds at + * their reset values on these early controllers. + */ + txdctl = 0; + break; + case e1000_82540: + case e1000_82545: + case e1000_82545_rev_3: + case e1000_82546: + case e1000_82546_rev_3: + case e1000_82541: + case e1000_82541_rev_2: + case e1000_82547: + case e1000_82547_rev_2: + break; + default: + KASSERT(0, ("%s: unsupported MAC type %d", __func__, + hw->mac.type)); + break; + } + + return (txdctl); +} + /********************************************************************* * * Enable transmit unit. @@ -3736,16 +3804,15 @@ em_initialize_transmit_unit(if_ctx_t ctx) E1000_READ_REG(hw, E1000_TDBAL(i)), E1000_READ_REG(hw, E1000_TDLEN(i))); - txdctl = 0; /* clear txdctl */ - txdctl |= 0x1f; /* PTHRESH */ - txdctl |= 1 << 8; /* HTHRESH */ - txdctl |= 1 << 16;/* WTHRESH */ if (hw->mac.type < igb_mac_min) { - txdctl |= 1 << 22; /* Reserved bit must always be 1 */ - txdctl |= E1000_TXDCTL_GRAN; - txdctl |= 1 << 25; /* LWTHRESH */ - } else + txdctl = em_legacy_txdctl(hw); + } else { + txdctl = 0; + txdctl |= 0x1f; /* PTHRESH */ + txdctl |= 1 << 8; /* HTHRESH */ + txdctl |= 1 << 16; /* WTHRESH */ txdctl |= E1000_TXDCTL_QUEUE_ENABLE; + } E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); } diff --git a/sys/dev/e1000/if_em.h b/sys/dev/e1000/if_em.h index 0f2d7baafdc8..0c61261a5af6 100644 --- a/sys/dev/e1000/if_em.h +++ b/sys/dev/e1000/if_em.h @@ -293,6 +293,9 @@ #define PCICFG_DESC_RING_STATUS 0xe4 #define FLUSH_DESC_REQUIRED 0x100 +#define EM_TX_PTHRESH 31 +#define EM_TX_HTHRESH 1 +#define EM_TX_WTHRESH 1 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ ((hw->mac.type <= e1000_82576) ? 16 : 8))