git: e2aff50727cb - main - igc: Correct descriptor control programming

The branch main has been updated by kbowling:

URL: https://cgit.FreeBSD.org/src/commit/?id=e2aff50727cbe4cb5e99f825c2c6bd8a4915de67

commit e2aff50727cbe4cb5e99f825c2c6bd8a4915de67
Author:     Kevin Bowling <kbowling@FreeBSD.org>
AuthorDate: 2026-08-08 11:30:40 +0000
Commit:     Kevin Bowling <kbowling@FreeBSD.org>
CommitDate: 2026-08-08 15:51:06 +0000

    igc: Correct descriptor control programming
    
    The transmit-ring setup was copied from the e1000 path.  On I225
    and I226, bits 22 through 24 are reserved and bit 25 enables the
    queue; it is not a legacy low-water threshold.  Correct the field
    masks, remove the nonapplicable legacy definitions, and program only
    defined fields.
    
    Use PTHRESH=8 and HTHRESH=1.  Keep WTHRESH at zero so the hardware
    honors sparse RS descriptors issued by iflib.  Linux and DPDK use a
    writeback threshold of 16, but request status on every packet.  A
    nonzero threshold makes hardware ignore individual RS bits and is
    unsuitable for the iflib completion model.
    
    The receive-ring setup likewise used a magic mask that left bit 20
    of the five-bit WTHRESH field untouched.  Define the receive threshold
    fields and replace them exactly before installing the established
    PTHRESH=8, HTHRESH=8, WTHRESH=4 policy.
    
    MFC after:      2 weeks
---
 sys/dev/igc/if_igc.c      | 19 +++++++------------
 sys/dev/igc/igc_defines.h | 16 ++++++++--------
 2 files changed, 15 insertions(+), 20 deletions(-)

diff --git a/sys/dev/igc/if_igc.c b/sys/dev/igc/if_igc.c
index 84012414ec27..a06caaaceeab 100644
--- a/sys/dev/igc/if_igc.c
+++ b/sys/dev/igc/if_igc.c
@@ -2259,13 +2259,9 @@ igc_initialize_transmit_unit(if_ctx_t ctx)
 		    IGC_READ_REG(&sc->hw, IGC_TDBAL(i)),
 		    IGC_READ_REG(&sc->hw, IGC_TDLEN(i)));
 
-		txdctl = 0; /* clear txdctl */
-		txdctl |= 0x1f; /* PTHRESH */
-		txdctl |= 1 << 8; /* HTHRESH */
-		txdctl |= 1 << 16;/* WTHRESH */
-		txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
-		txdctl |= IGC_TXDCTL_GRAN;
-		txdctl |= 1 << 25; /* LWTHRESH */
+		/* WTHRESH must be zero when iflib uses sparse RS. */
+		txdctl = IGC_TX_PTHRESH | (IGC_TX_HTHRESH << 8) |
+		    IGC_TXDCTL_QUEUE_ENABLE;
 
 		IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl);
 	}
@@ -2393,11 +2389,10 @@ igc_initialize_receive_unit(if_ctx_t ctx)
 		IGC_WRITE_REG(hw, IGC_RDT(i), 0);
 		/* Enable this Queue */
 		rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i));
-		rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;
-		rxdctl &= 0xFFF00000;
-		rxdctl |= IGC_RX_PTHRESH;
-		rxdctl |= IGC_RX_HTHRESH << 8;
-		rxdctl |= IGC_RX_WTHRESH << 16;
+		rxdctl &= ~(IGC_RXDCTL_PTHRESH | IGC_RXDCTL_HTHRESH |
+		    IGC_RXDCTL_WTHRESH);
+		rxdctl |= IGC_RX_PTHRESH | (IGC_RX_HTHRESH << 8) |
+		    (IGC_RX_WTHRESH << 16) | IGC_RXDCTL_QUEUE_ENABLE;
 		IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl);
 	}
 
diff --git a/sys/dev/igc/igc_defines.h b/sys/dev/igc/igc_defines.h
index 3e6309176204..9fc1c72022c3 100644
--- a/sys/dev/igc/igc_defines.h
+++ b/sys/dev/igc/igc_defines.h
@@ -551,15 +551,15 @@
 /* IGC_EITR_CNT_IGNR is only for 82576 and newer */
 #define IGC_EITR_CNT_IGNR	0x80000000 /* Don't reset counters on write */
 
+/* Receive Descriptor Control */
+#define IGC_RXDCTL_PTHRESH	0x0000001F /* RXDCTL Prefetch Threshold */
+#define IGC_RXDCTL_HTHRESH	0x00001F00 /* RXDCTL Host Threshold */
+#define IGC_RXDCTL_WTHRESH	0x001F0000 /* RXDCTL Writeback Threshold */
+
 /* Transmit Descriptor Control */
-#define IGC_TXDCTL_PTHRESH	0x0000003F /* TXDCTL Prefetch Threshold */
-#define IGC_TXDCTL_HTHRESH	0x00003F00 /* TXDCTL Host Threshold */
-#define IGC_TXDCTL_WTHRESH	0x003F0000 /* TXDCTL Writeback Threshold */
-#define IGC_TXDCTL_GRAN		0x01000000 /* TXDCTL Granularity */
-#define IGC_TXDCTL_FULL_TX_DESC_WB	0x01010000 /* GRAN=1, WTHRESH=1 */
-#define IGC_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
-/* Enable the counting of descriptors still to be processed. */
-#define IGC_TXDCTL_COUNT_DESC	0x00400000
+#define IGC_TXDCTL_PTHRESH	0x0000001F /* TXDCTL Prefetch Threshold */
+#define IGC_TXDCTL_HTHRESH	0x00001F00 /* TXDCTL Host Threshold */
+#define IGC_TXDCTL_WTHRESH	0x001F0000 /* TXDCTL Writeback Threshold */
 
 /* Flow Control Constants */
 #define FLOW_CONTROL_ADDRESS_LOW	0x00C28001