git: e38e04a0ba3f - main - arm64: Add more counter/timer registers

The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=e38e04a0ba3fdcdc2f3238bf4d962f65fadf527f

commit e38e04a0ba3fdcdc2f3238bf4d962f65fadf527f
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2025-09-22 17:08:25 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2025-09-23 17:08:36 +0000

    arm64: Add more counter/timer registers
    
    These will be used to support the Enhanced Counter Virtualization
    Extensions: FEAT_ECV and FEAT_ECV_POFF. The former adds
    Self-Synchronized registers, and the latter adds support for an offset
    for the physical counter.
    
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D51819
---
 sys/arm64/include/armreg.h | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index c2065fdb3f8c..da051e8f7c8a 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -232,6 +232,14 @@
 #define	CNTP_CTL_IMASK		(1 << 1)
 #define	CNTP_CTL_ISTATUS	(1 << 2)
 
+/* CNTP_CTL_EL02 - Counter-timer Physical Timer Control register */
+#define	CNTP_CTL_EL02_REG	MRS_REG_ALT_NAME(CNTP_CTL_EL02)
+#define	CNTP_CTL_EL02_op0	3
+#define	CNTP_CTL_EL02_op1	5
+#define	CNTP_CTL_EL02_CRn	14
+#define	CNTP_CTL_EL02_CRm	2
+#define	CNTP_CTL_EL02_op2	1
+
 /* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */
 #define	CNTP_CVAL_EL0_op0	3
 #define	CNTP_CVAL_EL0_op1	3
@@ -239,6 +247,14 @@
 #define	CNTP_CVAL_EL0_CRm	2
 #define	CNTP_CVAL_EL0_op2	2
 
+/* CNTP_CVAL_EL02 - Counter-timer Physical Timer CompareValue register */
+#define	CNTP_CVAL_EL02_REG	MRS_REG_ALT_NAME(CNTP_CVAL_EL02)
+#define	CNTP_CVAL_EL02_op0	3
+#define	CNTP_CVAL_EL02_op1	5
+#define	CNTP_CVAL_EL02_CRn	14
+#define	CNTP_CVAL_EL02_CRm	2
+#define	CNTP_CVAL_EL02_op2	2
+
 /* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */
 #define	CNTP_TVAL_EL0_op0	3
 #define	CNTP_TVAL_EL0_op1	3
@@ -254,6 +270,14 @@
 #define	CNTPCT_EL0_CRm		0
 #define	CNTPCT_EL0_op2		1
 
+/* CNTPCTSS_EL0 - Counter-timer Self-Synchronized Physical Count register */
+#define	CNTPCTSS_EL0_REG	MRS_REG_ALT_NAME(CNTPCTSS_EL0)
+#define	CNTPCTSS_EL0_op0	3
+#define	CNTPCTSS_EL0_op1	3
+#define	CNTPCTSS_EL0_CRn	14
+#define	CNTPCTSS_EL0_CRm	0
+#define	CNTPCTSS_EL0_op2	5
+
 /* CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register */
 #define	CNTV_CTL_EL0_op0	3
 #define	CNTV_CTL_EL0_op1	3
@@ -282,6 +306,14 @@
 #define	CNTV_CVAL_EL02_CRm	3
 #define	CNTV_CVAL_EL02_op2	2
 
+/* CNTVCTSS_EL0 - Counter-timer Self-Synchronized Virtual Count register */
+#define	CNTVCTSS_EL0_REG	MRS_REG_ALT_NAME(CNTVCTSS_EL0)
+#define	CNTVCTSS_EL0_op0	3
+#define	CNTVCTSS_EL0_op1	3
+#define	CNTVCTSS_EL0_CRn	14
+#define	CNTVCTSS_EL0_CRm	0
+#define	CNTVCTSS_EL0_op2	6
+
 /* CONTEXTIDR_EL1 - Context ID register */
 #define	CONTEXTIDR_EL1_REG	MRS_REG_ALT_NAME(CONTEXTIDR_EL1)
 #define	CONTEXTIDR_EL1_op0	3