git: 6de1c50e78a8 - main - uart: provide and use default rclk for JH7110 UART

The branch main has been updated by mhorne:

URL: https://cgit.FreeBSD.org/src/commit/?id=6de1c50e78a826abc08660e4c3ac10f1ddba9ba2

commit 6de1c50e78a826abc08660e4c3ac10f1ddba9ba2
Author:     Mitchell Horne <mhorne@FreeBSD.org>
AuthorDate: 2025-10-14 18:02:40 +0000
Commit:     Mitchell Horne <mhorne@FreeBSD.org>
CommitDate: 2025-10-31 15:30:02 +0000

    uart: provide and use default rclk for JH7110 UART
    
    A regression in the u-boot-provided JH7110 device tree leaves the uart
    incorrectly configured.
    
    The issue arises when a baud rate is specified ('current-speed'
    property), but the rclk value is not ('clock-frequency'). Previous
    releases, e.g. v2025.04, provided both.
    
    The alternative way to retrieve this value is to query the parent clock,
    but our clk framework is not available during early console probing and
    configuration.
    
    In this instance, we end up defaulting to DEFAULT_RCLK in ns8250_init(),
    which is the wrong value. The relevant uart class (uart_snps) should
    provide a default rclk in its definition, but it does not. Add a new
    variant class with the correct default rclk of 24000000.
    
    Finally, uart_cpu_fdt_probe() needs to be updated to actually query this
    default value when it does not find a 'clock-frequency' property. This
    was simply missing; the ACPI uart bus behaves identically, see
    uart_acpi_probe().
    
    PR:             289978
    Reported by:    rdunkle@smallcatbrain.com
    MFC after:      1 week
    Sponsored by:   The FreeBSD Foundation
    Differential Revision:  https://reviews.freebsd.org/D53119
---
 sys/dev/uart/uart_bus_fdt.c  |  6 ++++++
 sys/dev/uart/uart_dev_snps.c | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/sys/dev/uart/uart_bus_fdt.c b/sys/dev/uart/uart_bus_fdt.c
index 431f2962adb2..e9a7e04e4e0c 100644
--- a/sys/dev/uart/uart_bus_fdt.c
+++ b/sys/dev/uart/uart_bus_fdt.c
@@ -238,6 +238,12 @@ uart_cpu_fdt_probe(struct uart_class **classp, bus_space_tag_t *bst,
 			clk = 0;
 	}
 
+	/*
+	 * Grab the default rclk from the uart class.
+	 */
+	if (clk == 0)
+		clk = class->uc_rclk;
+
 	/*
 	 * Retrieve serial attributes.
 	 */
diff --git a/sys/dev/uart/uart_dev_snps.c b/sys/dev/uart/uart_dev_snps.c
index 6067920e3c2a..0372a220282b 100644
--- a/sys/dev/uart/uart_dev_snps.c
+++ b/sys/dev/uart/uart_dev_snps.c
@@ -113,7 +113,17 @@ struct uart_class uart_snps_class = {
 	.uc_rclk = 0,
 };
 
+struct uart_class uart_snps_jh7110_class = {
+	"snps",
+	snps_methods,
+	sizeof(struct snps_softc),
+	.uc_ops = &uart_ns8250_ops,
+	.uc_range = 8,
+	.uc_rclk = 24000000,
+};
+
 static struct ofw_compat_data compat_data[] = {
+	{ "starfive,jh7110-uart",	(uintptr_t)&uart_snps_jh7110_class },
 	{ "snps,dw-apb-uart",		(uintptr_t)&uart_snps_class },
 	{ "marvell,armada-38x-uart",	(uintptr_t)&uart_snps_class },
 	{ NULL,				(uintptr_t)NULL }